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Freescale Semiconductor Data Sheet: Advance Information
Document Number: IMX51AEC Rev. 1, 11/2009
IMX51A
i.MX51A Automotive and Infotainment Applications Processors
Package Information Plastic Package Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information See Table 1 on page 2 for ordering information.
1
Introduction
1
The MCIMX51A (i.MX51A) Automotive Infotainment Processor represents Freescale Semiconductor's latest addition to a growing family of multimedia focused products offering high performance processing with a high degree of functional integration, aimed at the growing automotive infotainment market. This device includes two graphics processors, 720p video processing, dual display, and many I/Os. The i.MX51A processor features Freescale's advanced implementation of the ARM Cortex A8TM core, targeting speeds up to 600 MHz with 200 MHz I/O bus clock DDR2 and mobileDDR. This device is well-suited for graphics rendering for HMI and navigation, high performance speech processing with large data bases, video processing and display, audio playback and ripping, and many other applications.
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Special Signal Considerations. . . . . . . . . . . . . . . . 11 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Supply Power-Up/Power-Down Requirements and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Output Buffer Impedance Characteristics . . . . . . . 26 3.5 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 29 3.6 Module Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 External Peripheral Interfaces . . . . . . . . . . . . . . . . 58 Package Information and Contact Assignments . . . . . . 135 4.1 19 x 19 mm Package Information . . . . . . . . . . . . 135 4.2 19 x 19 mm, 0.8 Pitch Ball Map. . . . . . . . . . . . . . 153 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2009. All rights reserved. Preliminary--Subject to Change Without Notice
Introduction
Features of the i.MX51A processor include the following: * Smart Speed Technology--The i.MX51A device has power management throughout the IC that enables the rich suite of multimedia feature and peripherals to achieve minimum power consumption in both active and various low power modes. Smart Speed Technology enables the designer to deliver a feature-rich product that requires levels of power that are far less than industry expectations. * Multimedia--The multimedia performance of the ARM Cortex A8 is enhanced with a multi-level cache system, a Multi-standard Hardware Video CODECs, autonomous image processing unit, multi-standard audio CODECs, Neon (an advanced SIMD, 32 bit single-precision floating point support and vector floating point co-processor), and a programmable smart DMA controller. * Powerful Graphics Acceleration--The i.MX51A processor has an integrated Graphics Processing Unit which includes an OpenGl 2.0 GPU that provides 27Mtri/sec, 166Mpix/s, and 664Mpix/s z-plane performance. Silicon version 2.0 of the i.MX51A device includes an independent OpenVG GPU operating at166Mpix/s. * Interface Flexibility--The i.MX51A processor supports connections to all popular types of external memories: mobile DDR, DDR2, PSRAM, NOR Flash, NAND Flash (MLC and SLC), and OneNAND (managed NAND). The i.MX51A processor also includes a rich multimedia suite of interfaces: LCD controller for two displays, CMOS sensor interface, High-Speed USB On-The-Go plus three High-Speed USB hosts, high-speed MMC/SDIO, Fast Ethernet controller, UART, I2C, I2S (SSI), and others.
1.1
Ordering Information
Table 1. Ordering Information
Table 1 provides the ordering information.
Part Number1
Mask Set
Features
Junction Temperature Range (C) -40 to 125 -40 to 125 -40 to 125
Package 2
PCIMX511AJM6C PCIMX514AJM6C PCIMX516AJM6C
1 2
M77X
No hardware video codecs No display or camera interfaces No hardware video codecs Full specification
19 x 19 mm, 0.8 mm pitch BGA Case 2017 19 x 19 mm, 0.8 mm pitch BGA Case 2017 19 x 19 mm, 0.8 mm pitch BGA Case 2017
M77X
M77X
Part numbers with a PC prefix indicate non-production engineering parts. Case 2017 and Case 2058 are RoHS compliant, lead-free, MSL = 3.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Introduction
1.2
Block Diagram
TV-Out Access. Conn.
Figure 1 shows the functional modules of the processor.
Digital Audio DDR Memory NOR/Nand Battery Ctrl Device Flash USB Dev/Host Camera 1 Camera 2 LCD Display 1 LCD Display 2 ATA HDD
External Memory I/F
USB PHY
Application Processor Domain (AP)
TV Encoder
USB OTG + 3 HS Ports
Smart DMA (SDMA) Ethernet
Image Processing Subsystem
AP Peripherals eCSPI (2) CSPI UART (3) AUDMUX
SPBA AXI and AHB Switch Fabric Internal RAM (128 Kbytes) Boot ROM
ARM Cortex A8 Platform ARM Cortex A8
Neon and VFP
I2C(2),HSI 2C 1-WIRE PWM (2) IIM IOMUXC KPP GPIOx32 (4) SJC SSI (3) FIRI Debug DAP TPIU CTI (2)
SDMA Peripherals
eSDHC (4) UART SPDIF Tx FEC SSI eCSPI (1 of 2) SIM P-ATA
Freescale Semiconductor Preliminary--Subject to Change Without Notice
GPS RF/IF ICs SIM Audio/Power Management
L1 I/D cache L2 cache ETM, CTI0,1
Security SAHARA Lite RTIC SCC SRTC CSU TZIC Timers WDOG (2) GPT EPIT (2)
Video Proc. Unit (VPU) 3D Graphics Proc Unit (GPU)
Fuse Box
Graphics Memory (128 Kbytes) 2D Graphics Proc Unit (GPU2D)
Clock and Reset PLL (3) CCM GPC SRC XTALOSC CAMP (2)
JTAG
IrDA XVR
Bluetooth
WLAN
USB-OTG XVR
MMC/SDIO
Keypad
Figure 1. Functional Block Diagram
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Features
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Features
Table 2. i.MX51A Digital and Analog Modules
The i.MX51A processor contains a large number of digital and analog modules that are described in Table 2.
Block Mnemonic 1-WIRE ARM Cortex A8TM
Block Name 1-Wire Interface
Subsystem Connectivity Peripherals
Brief Description 1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502. The ARM Cortex A8TM Core Platform consists of the ARM Cortex A8TM processor version r2p5 (with TrustZone) and its essential sub-blocks. It contains the Level 2 Cache Controller, 32-Kbyte L1 instruction cache, 32-Kbyte L1 data cache, and a 256-Kbyte L2 cache. The platform also contains an Event Monitor and Debug modules. It also has a NEON co-processor with SIMD media processing architecture, register file with 32 x 64-bit general-purpose registers, an Integer execute pipeline (ALU, Shift, MAC), dual, single-precision floating point execute pipeline (FADD, FMUL), load/store and permute pipeline and a Non-Pipelined Vector Floating Point (VFP) co-processor (VFPv3). The elements of the audio subsystem are three Synchronous Serial Interfaces (SSI1-3), a Digital Audio Mux (AUDMUX), and Digital Audio Out (SPDIF TX). See the specific interface listings in this table. The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs). The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports.
ARM Cortex ARM A8TM Platform
Audio Subsystem AUDMUX
Audio Subsystem Digital Audio Mux
Multimedia Peripherals Multimedia Peripherals
CCM GPC SRC CSPI-1, eCSPI-2 eCSPI-3 CSU
These modules are responsible for clock and reset distribution in the system, Clock Control Clocks, and also for system power management. The modules include three PLLs and Resets, and Module Global Power Power Control a Frequency Pre-Multiplier (FPM). Controller System Reset Controller Configurable SPI, Enhanced CSPI Central Security Unit Connectivity Peripherals Full-duplex enhanced Synchronous Serial Interface, with data rate up to 66.5Mbit/s (for eCSPI, master mode). It is configurable to support Master/Slave modes, four chip selects to support multiple peripherals. The Central Security Unit (CSU) is responsible for setting comprehensive security policy within the i.MX51A platform, and for sharing security information between the various security modules. The Security Control Registers (SCR) of the CSU are set during boot time by the High Assurance Boot (HAB) code and are locked to prevent further writing. The Debug System provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, cross-system triggers, counters, and sequencers.
Security
Debug System
Debug System
System Control
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic EMI Block Name External Memory Interface Subsystem Connectivity Peripherals Brief Description The EMI is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels: fast memories (Mobile DDR, DDR2) channel, slow memories (NOR-FLASH/PSRAM/NAND-FLASH etc.) channel, internal memory (RAM, ROM) channel and graphical memory (GMEM) Channel. In order to increase the bandwidth performance, the EMI separates the buffering and the arbitration between different channels so parallel accesses can occur. By separating the channels, slow accesses do not interfere with fast accesses. EMI features: * 64-bit and 32-bit AXI ports * Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (Read or Write) was the last access * Flexible bank interleaving * Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400) * Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400) * Supports up to 2 Gbit Mobile DDR memories * Supports 16-bit (in muxed mode only) PSRAM memories (sync and async operating modes), at slow frequency, for debugging purposes * Supports 32-bit NOR-Flash memories (only in muxed mode), at slow frequencies for debugging purposes * Supports 4/8-ECC, page sizes of 512 Bytes, 2 KBytes and 4 KBytes * NAND-Flash (including MLC) * Multiple chip selects * Enhanced Mobile DDR memory controller, supporting access latency hiding * Supports watermarking for security (Internal and external memories) * Supports Samsung OneNANDTM (only in muxed I/O mode) Each EPIT is a 32-bit "set and forget" timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly. The features of the eSDHC module, when serving as host, include the following: * Conforms to SD Host Controller Standard Specification version 2.0 * Compatible with the MMC System Specification version 4.2 * Compatible with the SD Memory Card Specification version 2.0 * Compatible with the SDIO Card Specification version 1.2 * Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC and MMC RS cards * Configurable to work in one of the following modes: --SD/SDIO 1-bit, 4-bit --MMC 1-bit, 4-bit, 8-bit * Full-/high-speed mode * Host clock frequency variable between 32 kHz to 52 MHz * Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines * Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
EPIT-1 EPIT-2
Enhanced Periodic Interrupt Timer
Timer Peripherals
eSDHC-1 eSDHC-2 eSDHC-3
Connectivity Enhanced Peripherals Multi-Media Card/ Secure Digital Host Controller
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic eSDHC-4 (muxed with P-ATA) Block Name Subsystem Brief Description Can be configured as eSDHC (see above) and is muxed with the P-ATA interface.
Connectivity Enhanced Peripherals Multi-Media Card/ Secure Digital Host Controller Fast Ethernet Connectivity Controller Peripherals
FEC
The Ethernet Media Access Controller (MAC) is designed to support both 10 Mbps and 100 Mbps ethernet/IEEE Std 802.3TM networks. An external transceiver interface and transceiver function are required to complete the interface to the media. Fast Infra-Red Interface
FIRI
Fast Infra-Red Interface General Purpose I/O Modules General Purpose Timer
Connectivity Peripherals System Control Peripherals Timer Peripherals
GPIO-1 GPIO-2 GPIO-3 GPIO-4 GPT
These modules are used for general purpose input/output to external ICs. Each GPIO module supports up to 32 bits of I/O.
Each GPT is a 32-bit "free-running" or "set and forget" mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in "set and forget" mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock. The GPU provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution. It supports color representation up to 32 bits per pixel. The GPU with its 128 KByte memory enables high performance mobile 3D and 2D vector graphics at rates up to 27 Mtriangles/sec, 166 M pixels/sec, 664 Mpixels/sec (Z). The GPU2D provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD720 resolution. I2C provides serial interface for controlling peripheral devices. Data rates of up to 400 Kbps are supported by two of the I2C ports. Data rates of up to 3.4 Mbps (I2C Specification v2.1) are supported by the HS-I2C. Note: See the errata for the HS-I2C in the i.MX51 Chip Errata. The two standard I2C modules have no errata.
GPU
Graphics Processing Unit
Multimedia Peripherals
GPU2D
Multimedia Graphics Peripherals Processing Unit-2D Ver. 1 I2C Interface Connectivity Peripherals
I2C-1 I2C-2 HS-I2C
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic IIM Block Name IC Identification Module Subsystem Security Brief Description The IC Identification Module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module. This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable. IPU enables connectivity to displays and image sensors, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces. * Legacy Interfaces * Analog TV interfaces (through a TV encoder bridge) The processing includes: * Support for camera control * Image enhancement: color adjustment and gamut mapping, gamma correction and contrast enhancement, sharpening and noise reduction * Video/graphics combining * Support for display backlight reduction * Image conversion--resizing, rotation, inversion and color space conversion * Synchronization and control capabilities, allowing autonomous operation. * Hardware de-interlacing support KPP Keypad Port Connectivity Peripherals The KPP supports an 8 x 8 external keypad matrix. The KPP features are as follows: * Open drain design * Glitch suppression circuit design * Multiple keys detection * Standby key press detection The P-ATA block is an AT attachment host interface. Its main use is to interface with hard disc drives and optical disc drives. It interfaces with the ATA-5 (UDMA-4) compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side. This is muxed with eSDHC-4 interfaces. The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound. Unified RAM, can be split between Secure RAM and Non-Secure RAM Supports secure and regular Boot Modes
IOMUXC
IOMUX Control Image Processing Unit
System Control Peripherals Multimedia Peripherals
IPU
P-ATA (Muxed Parallel ATA with eSDHC-4
Connectivity Peripherals
PWM-1 PWM-2 RAM 128 Kbytes ROM 36 Kbytes
Pulse Width Modulation Internal RAM Boot ROM
Connectivity Peripherals Internal Memory Internal Memory
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic RTIC Block Name Real Time Integrity Checker Subsystem Security Brief Description Protecting read-only data from modification is one of the basic elements in trusted platforms. The Run-Time Integrity Checker v3 (RTICv3) module, is a data monitoring device responsible for ensuring that memory content is not corrupted during program execution. The RTICv3 mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The RTICv3's purpose is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement, and assist with boot authentication. SAHARA (Symmetric/Asymmetric Hashing and Random Accelerator) is a security co-processor. It implements symmetric encryption algorithms, (AES, DES, 3DES, and RC4), public key algorithms, hashing algorithms (MD5, SHA-1, SHA-224, and SHA-256), and a hardware random number generator. It has a slave IP bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory. The Security Controller is a security assurance hardware module designed to safely hold sensitive data such as encryption keys, digital right management (DRM) keys, passwords, and biometrics reference data. The SCC monitors the system's alert signal to determine if the data paths to and from it are secure--that is, cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal RAM. The SCC also features a Key Encryption Module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data. The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing. The SDMA features list is as follows: * Powered by a 16-bit instruction-set micro-RISC engine * Multi-channel DMA supports up to 32 time-division multiplexed DMA channels * 48 events with total flexibility to trigger any combination of channels * Memory accesses including linear, FIFO, and 2D addressing * Shared peripherals between ARM Cortex A8TM and SDMA * Very fast context-switching with two-level priority-based preemptive multi-tasking * DMA units with auto-flush and prefetch capability * Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address) * DMA ports can handle unit-directional and bi-directional flows (copy mode) * Up to 8-word buffer for configurable burst transfers for EMI * Support of byte-swapping and CRC calculations * A library of scripts and API are available The SIM is an asynchronous interface with additional features for allowing communication with Smart Cards conforming to the ISO 7816 specification. The SIM is designed to facilitate communication to SIM cards or pre-paid phone cards.
SAHARA Lite SAHARA security accelerator Lite
Security
SCC
Security Controller
Security
SDMA
Smart Direct Memory Access
System Control Peripherals
SIM
Subscriber Identity Module Interface
Connectivity Peripherals
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic SJC Block Name Secure JTAG Interface Subsystem System Control Peripherals Brief Description JTAG manipulation is a known hacker's method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus. The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden. In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX51A processor incorporates a mechanism for regulating JTAG access. The i.MX51A Secure JTAG Controller provides four different JTAG security modes that can be selected via e-fuse configuration. SPBA Shared Peripheral Bus Arbiter Sony Philips Digital Interface Secure Real Time Clock System Control Peripherals Multimedia Peripherals Security SPBA (Shared Peripheral Bus Arbiter) is a two-to-one IP bus interface (IP bus) arbiter. A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Only the transmitter functionality is supported. The SRTC incorporates a special System State Retention Register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized even if all other supply rails are shut down. The power for this block comes from NVCC_SRTC_POW supply. When this supply is driven by the MC13892 power management controller, this block can be power backed up via the coin-cell feature of the MC13892.This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication). The SSI is a full-duplex synchronous interface used on the i.MX51A processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX which interfaces to the i.MX51 system memory. The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options. Each SSI has two pairs of 8x24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two timeslots are being used simultaneously. The TVE is implemented in conjunction with the Image Processing Unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports the following analog video outputs: composite, S-video, and component video up to HD720p/1080i.
SPDIF
SRTC
SSI-1 SSI-2 SSI-3
I2S/SSI/AC97 Connectivity Interface Peripherals
TVE
TV Encoder
Multimedia
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic TZIC Block Name TrustZone Aware Interrupt Controller UART Interface Subsystem ARM/Control Brief Description The TrustZone Interrupt Controller (TZIC) collects interrupt requests from all i.MX51A sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported. Each of the UART modules supports the following serial data transmit/receive protocols and configurations: * 7 or 8 bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none) * Programmable baud rates up to 4 MHz. This is a higher max baud rate relative to the 1.875 MHz, which is stated by the TIA/EIA-232-F standard and previous Freescale UART modules. * 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud * IrDA 1.0 support (up to SIR speed of 115200 bps) * Option to operate as 8-pins full UART, DCE, or DTE USB-OTG contains one high-speed OTG module, which is internally connected to the on-chip HS USB PHY. There are an additional three high-speed host modules that require external USB PHYs. A high-performing video processing unit (VPU), which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring. VPU Features: * MPEG-4 decode: 720p, 30 fps, simple profile and advanced simple profile * MPEG-4 encode: D1, 25/30 fps, simple profile * H.263 decode: 720p, 30 fps, profile 3 * H.263 encode: D1, 25/30 fps, profile 3 * H.264 decode: 720p, 30 fps, baseline, main, and high profile * H.264 encode: D1, 25/30 fps, baseline profile * MPEG-2 decode: 720p, 30 fps, MP-ML * MPEG-2 encode: D1, 25/30 fps, MP-ML (in software with partial acceleration in hardware) * VC-1 decode: 720p, 30 fps, simple, main, and advanced profile * DivX decode: 720p, 30 fps versions 3, 4, and 5 * RV10 decode: 720p, 30 fps * MJPEG decode: 32 Mpix/s * MJPEG encode: 64 Mpix/s The Watch Dog Timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the WDOG line.
UART-1 UART-2 UART-3
Connectivity Peripherals
USB
USB 2.0 High-Speed OTG and 3x Hosts Video Processing Unit
Connectivity Peripherals
VPU
Multimedia Peripherals
WDOG-1
Watch Dog
Timer Peripherals
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Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block Mnemonic WDOG-2 (TZ) Block Name Watch Dog (TrustZone) Subsystem Timer Peripherals Brief Description The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system's security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode. If it is still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. The XTALOSC module allows connectivity to an external crystal.
XTALOSC
Crystal Oscillator I/F
Clocking
2.1
Special Signal Considerations
Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order. The package contact assignments are found in Section 4, "Package Information and Contact Assignments." Signal descriptions are defined in the i.MX51 reference manual.
Table 3. Special Signal Considerations
Signal Name CKIH1, CKIH2 Remarks Inputs feeding CAMPs (Clock Amplifiers) that have on-chip ac coupling precluding the need for external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter external oscillators to feed CKIH1 or CKIH2 (while not required) can be an advantage if low jitter or special frequency clock sources are required by modules driven by CKIH1 or CKIH2. See CCM chapter in the i.MX51 reference manual for details on the respective clock trees. After initialization, the CAMPs could be disabled (if not used) by CCM registers (CCR CAMPx_EN field). If disabled, the on-chip CAMP output is low; the input is irrelevant. If unused, the user should tie CKIH1/CKIH2 to GND for best practice. Clock Source Select is the input that selects the default reference clock source providing input to the DPLLs. To use a reference in the megahertz range per Table 8, tie CLK_SS to GND to select EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3 to select CKIL. After initialization, the reference clock source can be changed (initial setting is overwritten). Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly to GND or NVCC_PER3. If a series resistor is used its value must be 4.7 k. The user should bypass this reference with an external 0.1 F capacitor tied to GND. If TV OUT is not used, float the COMP contact and ensure the DACs are powered down. Note: Previous engineering samples required this reference to be bypassed to a positive supply. These signals are reserved for Freescale manufacturing use only. User must tie both connections to GND. This signal is reserved for Freescale manufacturing use only. Users should float this output. This is a general-purpose input/output (GPIO3_12) on the NVCC_NANDF_A power rail.
CLK_SS
COMP
FASTR_ANA and FASTR_DIG GPANAIO GPIO_NAND
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Features
Table 3. Special Signal Considerations (continued)
Signal Name Remarks
IOB, IOG, IOR, IOB_BACK, These signals are analog TV outputs that should be tied to GND when not being used. IOG_BACK, and IOR_BACK JTAG_nnnn The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However, if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is followed. For example, do not use an external pull down on an input that has on-chip pull-up. JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and should be avoided. JTAG_MOD is referenced as SJC_MOD in the i.MX51 Reference Manual. Both names refer to the same signal. JTAG_MOD must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k) is allowed. NC PMIC_INT_REQ These signals are No Connect (NC) and should be floated by the user. When using the MC13892 power management IC, the PMIC_INT_REQ high-priority interrupt input on i.MX51 should be either floated or tied to NVCC_SRTC_POW with a 4.7 k to 68 k resistor. This avoids a continuous current drain on the real-time clock backup battery due to a 100 k on-chip pull-up resistor. PMIC_INT_REQ is not used by the Freescale BSP (board support package) software. The BSP requires that the general-purpose INT output from the MC13892 be connected to i.MX51 GPIO input GPIO1_8 configured to cause an interrupt that is not high-priority. The original intent was for PMIC_INT_REQ to be connected to a circuit that detects when the battery is almost depleted. In this case, the I/O must be configured as alternate mode 0 (ALT0 = power fail). This cold reset negative logic input resets all modules and logic in the IC. Note: The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage. This warm reset negative logic input resets all modules and logic except for the following: * Test logic (JTAG, IOMUXC, DAP) * SRTC * Memory repair - Configuration of memory repair per fuse settings * Cold reset logic of WDOG - Some WDOG logic is only reset by POR_B. See WDOG chapter in i.MX51 Reference Manual for details. Determines the reference current for the USB PHY bandgap reference. An external 6.04 k 1% resistor to GND is required. These sense lines provide the ability to sense actual on-chip voltage levels on their respective supplies. SGND monitors differentials of the on-chip ground versus an external power source. SVCC monitors on-chip VCC, and SVDDGP monitors VDDGP. Freescale recommends connection of the SVCC and SVDDGP signals to the feedback inputs of switching power-supplies or to test points. This signal is reserved for Freescale manufacturing use. The user should float this signal. TEST_MODE is for Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND.
POR_B
RESET_IN_B
RREFEXT SGND, SVCC, and SVDDGP
STR TEST_MODE
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Table 3. Special Signal Considerations (continued)
Signal Name VREF Remarks When using VREF with DDR-2 I/O, the nominal 0.9 V reference voltage must be half of the NVCC_EMI_DRAM supply. The user must tie VREF to a precision external resistor divider. Use a 1 k 0.5% resistor to GND and a 1 k 0.5% resistor to NVCC_EMI_DRAM. Shunt each resistor with a closely-mounted 0.1 F capacitor. To reduce supply current, a pair of 1.5 k 0.1% resistors can be used. Using resistors with recommended tolerances ensures the 2% VREF tolerance (per the DDR-2 specification) is maintained when four DDR-2 ICs plus the i.MX51 are drawing current on the resistor divider. Note: When VREF is used with mDDR this signal must be tied to GND. This signal determines the Triple Video DAC (TVDAC) reference voltage. The user must tie VREFOUT to an external 1.18 k 1% resistor to GND. This regulator is no longer used and should be floated by the user. The user should tie a fundamental-mode crystal across XTAL and EXTAL. The crystal must be rated for a maximum drive level of 100 W or higher. An ESR (equivalent series resistance) of 80 or less is recommended. Freescale BSP (Board Support Package) software requires 24 MHz on EXTAL. The crystal can be eliminated if an external 24 MHz oscillator is available. In this case, EXTAL must be directly driven by the external oscillator and XTAL is floated. The EXTAL signal level must swing from NVCC_OSC to GND. If the clock is used for USB, then there are strict jitter requirements: < 50 ps peak-to-peak below 1.2 MHz and < 100 ps peak-to-peak above 1.2 MHz for the USB PHY. The COSC_EN bit in the CCM (Clock Control Module) must be cleared to put the on-chip oscillator circuit in bypass mode which allows EXTAL to be externally driven. COSC_EN is bit 12 in the CCR register of the CCM.
VREFOUT VREG XTAL/EXTAL
Table 4. JTAG Controller Interface Summary
JTAG JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRSTB JTAG_DE_B JTAG_MOD I/O Type Input Input Input 3-state output Input Input/open-drain output Input On-chip Termination 100 k pull-down 47 k pull-up 47 k pull-up Keeper 47 k pull-up 47 k pull-up 100 k pull-down
3
3.1
Electrical Characteristics
Chip-Level Conditions
This section provides the device and module-level electrical characteristics for the i.MX51Aprocessor.
This section provides the device-level electrical characteristics for the IC. See Table 5 for a quick reference to the individual tables and sections.
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Electrical Characteristics
Table 5. i.MX51A Chip-Level Conditions
For these characteristics, ... Table 6, "Absolute Maximum Ratings" Table 7, "Thermal Resistance Data" Table 8, "i.MX51A Operating Ranges" Table 9, "Interface Frequency" Topic appears ... on page 14 on page 14 on page 15 on page 16
CAUTION Stresses beyond those listed under Table 6 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Table 8, "i.MX51A Operating Ranges," on page 15 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Table 6. Absolute Maximum Ratings
Parameter Description Peripheral Core Supply Voltage ARM Core Supply Voltage Supply Voltage (UHVIO, I2C) Supply Voltage (except UHVIO, USB VBUS Input/Output Voltage Range ESD Damage Immunity: Human Body Model (HBM) Charge Device Model (CDM) Storage Temperature Range Junction Temperature
1
Symbol VCC VDDGP Supplies denoted as I/O Supply
Min -0.3 -0.3 -0.5 -0.5 -- -0.5
Max 1.35 1.15 3.6 3.3 5.25 OVDD +0.31
Unit V V V V V V V
I2C)
Supplies denoted as I/O Supply VBUS Vin/Vout Vesd
-- -- TSTORAGE TJ -40 --
2000 500 125 1252
oC oC
The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in Table 111 on page 139. The maximum range can be superseded by the DC tables. 2 During the life of the device, T must be limited to a cumulative of 2% of the time over 105oC. J
Table 7 provides the thermal resistance data.
Table 7. Thermal Resistance Data
Rating Junction to Case1, 19 x 19 mm package
1
Board --
Symbol RJC
Value 6
Unit C/W
Rjc-x per JEDEC 51-12: The junction-to-case thermal resistance. The "x" indicates the case surface where Tcase is measured and through which 100% of the junction power is forced to flow due to the cold plate heat sink fixture placed either at the top (T) or bottom (B) of the package, with no board attached to the package.
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Electrical Characteristics
Table 8. i.MX51A Operating Ranges
Symbol VDDGP MCIMX51xA products Parameter ARM core supply voltage 0 < fARM 600 MHz ARM core supply voltage Stop mode VCC MCIMX51xA products Peripheral supply voltage High Performance Mode (HPM) The clock frequencies are derived from AXI and AHB buses using 133 or 166 MHz (as needed). The DDR clock rate is 200 MHz. Note: For detailed information about the use of 133 or 166 MHz clocks, refer to the i.MX51 Reference Manual. Peripheral supply voltage--Stop mode VDDA Memory arrays voltage--Run Mode Memory arrays voltage--Stop Mode VDD_DIG_PLL_A VDD_DIG_PLL_B VDD_ANA_PLL_A VDD_ANA_PLL_B NVCC_EMI NVCC_PER5 NVCC_PER10 NVCC_PER11 NVCC_PER12 NVCC_PER13 NVCC_PER14 NVCC_IPUx3 NVCC_PER3 NVCC_PER8 NVCC_PER9 NVCC_EMI_DRAM VDD_FUSE4 NVCC_NANDF_x5 NVCC_PER15 NVCC_PER17 PLL Digital supplies PLL Analog supplies GPIO EMI Supply and additional digital power supplies. Minimum1 0.95 0.93 1.175 Nominal2 1.0 0.95 1.225 Maximum1 1.1 1.05 1.275 Unit V V V
0.93 1.15 0.93 1.15 1.75 1.65
0.95 1.20 0.95 1.2 1.8 1.875 or 2.775
1.275 1.275 1.275 1.35 1.95 3.1
V V V V V V
GPIO IPU Supply and additional digital power supplies.
1.65
1.875 or 2.775
3.1
V
DDR and Fuse Read Supply Fusebox Program Supply (Write Only) Ultra High voltage I/O (UHVIO) supplies UHVIO_L UHVIO_H UHVIO_UH
1.65 3.0
1.8 -- --
1.95 3.3
V V V
1.65 2.5 3.0 2.25 2.69
1.875 2.775 3.3 2.5 2.75
1.95 3.1 3.6 2.75 2.91 V V
NVCC_USBPHY NVCC_OSC TVDAC_DHVDD, NVCC_TV_BACK, AHVDDRGB
USB_PHY analog supply, oscillator analog supply6 TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel
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Electrical Characteristics
Table 8. i.MX51A Operating Ranges (continued)
Symbol NVCC_HS4_1 NVCC_HS4_2 NVCC_HS6 NVCC_HS10 NVCC_I2C Parameter HS-GPIO additional digital power supplies Minimum1 1.65 Nominal2 -- Maximum1 3.1 Unit V
I2C and HS-I2C I/O Supply7
1.65 2.7
1.875 3.0 1.2 3.3 --
1.95 3.3 1.3 3.6 --
V
NVCC_SRTC_ POW VDDA33 VBUS
SRTC Core and I/O Supply (LVIO) USB PHY I/O analog supply See Table 6 on page 14 and Table 109 on page 135 for details. This is not a power supply.
1.1 3.0 --
V V --
1 2 3 4 5 6 7
Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops. The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than 50 mV. Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings. The NVCC_IPUx rails are isolated from one another. This allows the connection of different supply voltages for each one. For example, NVCC_IPU2 can operate at 1.8 V while NVCC_IPU4 operates at 3.0 V. In Read mode, Freescale recommends VDD_FUSE be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V-3.3 V) increases the possibility of inadvertently blowing fuses and is not recommended. The NAND Flash supplies are composed of three groups: A, B, and C. Each group can be powered with a different supply voltage. For example, NVCC_NANDF_A = 1.8 V, NVCC_NANDF_B = 3.0 V, NVCC_NANDF_C = 2.7 V. The analog supplies should be isolated in the application design. Use of series inductors is recommended. Operation of the HS-I2C and I2C is not guaranteed when operated between the supply voltages of 1.95 to 2.7 V.
Table 9. Interface Frequency
Parameter Description JTAG: TCK Operating Frequency CKIL: Operating Frequency CKIH: Operating Frequency XTAL Oscillator Symbol ftck fckil fckih fxtal Min Max Unit MHz kHz MHz MHz
See Table 86, "JTAG Timing," on page 117 See Table 61, "FPM Specifications," on page 67 See Table 34, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 35 22 27
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Electrical Characteristics
3.1.1
Supply Current
Table 10. Fuse Supply Current
Description Symbol Iprogram Min -- Typ 60 Max TBD Unit mA
eFuse Program Current.1 Current to required to program one eFuse bit: The associated VDD_FUSE supply per Table 8. eFuse Read Current2 Current necessary to read an 8-bit eFuse word
1 2
Iread
--
TBD
TBD
mA
The current Iprogram is only required during program time (tprogram). The current Iread is present for approximately TBD ns of the read access to the 8-bit word. The current is derived from the DDR supply (NVCC_EMI_DRAM).
Table 11 shows the current core consumption (not including I/O) of the i.MX51.
Table 11. i.MX51 Stop Mode Current and Power Consumption
Mode Stop Mode * External reference clocks gated * Power gating for ARM and processing units * Stop mode voltage Condition VDDGP = 0.95 V, VCC = 0.95 V, VDDA = 0.95 V ARM CORE in SRPG mode L1 and L2 caches power gated IPU in S&RPG mode VPU and GPU in PG mode All PLLs off, all CCM-generated clocks off CKIL input on with 32 kHz signal present All modules disabled USBPHY PLL off External (MHz) crystal and on-chip oscillator powered down (SBYOS bit asserted) No external resistive loads that cause current flow Standby voltage allowed (VSTBY bit is asserted) TA = 25C VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V ARM CORE in SRPG mode L1 and L2 caches power gated IPU in S&RPG mode VPU and GPU in PG mode All PLLs off, all CCM-generated clocks off CKIL input on with 32 kHz signal present All modules disabled. USBPHY PLL off External (MHz) crystal and on-chip oscillator powered down (SBYOS bit asserted) No external resistive loads that cause current flow TA = 25C Supply VDDGP VCC VDDA NVCC_OSC Total Nominal 0.18 0.35 0.15 0.012 0.66 mW Unit mA
Stop Mode * External reference clocks gated * Power gating for ARM and processing units * HPM voltage
VDDGP VCC VDDA NVCC_OSC Total
0.24 0.45 0.2 0.012 1.09
mA
mW
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Electrical Characteristics
Table 11. i.MX51 Stop Mode Current and Power Consumption (continued)
Mode Stop Mode * External reference clocks enabled * Power gating for ARM and processing units * HPM voltage Condition VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.20 V ARM CORE in SRPG mode L1 and L2 caches power gated IPU in S&RPG mode VPU and GPU in PG mode All PLLs off, all CCM-generated clocks off CKIL input on with 32 kHz signal present All modules disabled USBPHY PLL off External (MHz) crystal and on-chip oscillator powered and generating reference clock No external resistive loads that cause current flow TA = 25C Stop Mode * External reference clocks enabled * No power gating for ARM and processing units * HPM voltage VDDGP = 1.0 V, VCC = 1.225 V, VDDA = 1.2 V All PLLs off, all CCM-generated clocks off CKIL input on with 32 kHz signal present All modules disabled USBPHY PLL off External (MHz) crystal and on-chip oscillator powered and generating reference clock No external resistive loads that cause current flow TA = 25C VDDGP VCC VDDA NVCC_OSC Total 50 2 1.15 1.5 63 mW mA Supply VDDGP VCC VDDA NVCC_OSC Total Nominal 0.24 0.45 0.2 1.5 4.8 mW Unit mA
3.1.2
USB PHY Current Consumption
Table 12. USB PHY Current Consumption
Parameter Conditions RX Full Speed Typical @ 25 C 5.5 7 5 5 6.5 6.5 12 21 Max 6 8 6 6 7 7 13 22 mA mA Unit
Analog Supply VDDA33 (3.3 V) High Speed
TX RX TX RX
Full Speed Analog Supply NVCC_USBPHY (2.5 V) High Speed
TX RX TX
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Electrical Characteristics
Table 12. USB PHY Current Consumption (continued)
Parameter Conditions RX Full Speed Digital Supply VCC (1.2 V) High Speed VDDA33 + NVCC_USBPHY +VCC Suspend TX RX TX Typical @ 25 C 6 6 6 6 50 Max 7 7 7 7 100 A mA Unit
3.2
Supply Power-Up/Power-Down Requirements and Restrictions
The system design must comply with the power-up and power-down sequence guidelines as described in this section to guarantee reliable operation of the device. Any deviation from these sequences may result in the following situations: * Excessive current during power-up phase * Prevention of the device from booting * Irreversible damage to the i.MX51A processor (worst-case scenario)
3.2.1
Power-Up Sequence
Figure 2 shows the power-up sequence.
NVCC_SRTC_POW
VCC
VDDGP4
NVCC_EMI_DRAM
VDDA
NVCC_HS4_1 NVCC_HS4_2 NVCC_HS6 NVCC_HS10 NVCC_PERx2 NVCC_EMI NVCC_IPU NVCC_I2C
NVCC_NANDF_x NVCC_PER15 NVCC_PER17
AHVDDRGB NVCC_TV_BACK TVDAC_DHVDD VDD_DIG_PLL_A/B VDD_ANA_PLL_A/B NVCC_OSC NVCC_USBPHY VDDA33
VDD_FUSE1
1. VDD_FUSE should only be powered when writing. 2. NVCC_PERx refers to NVCC_PER 3, 5, 8, 9, 10, 11, 12, 13, 14. 3. No power-up sequence dependencies exist between the supplies shown in the block diagram shaded in gray. 4. There is no requirement for VDDGP to be preceded by any other power supply other than NVCC_SRTC_POW.
Figure 2. Power-Up Sequence
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Electrical Characteristics
NOTE The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail is at its working voltage.
3.2.2
Power-Down Sequence
The following power-down sequence is recommend for the i.MX51A processor: * To be provided.
3.3
I/O DC Parameters
This section includes the DC parameters of the following I/O types: * General Purpose I/O and High-Speed General Purpose I/O (GPIO/HSGPIO) * Double Data Rate 2 (DDR2) * Low Voltage I/O (LVIO) * Ultra High Voltage I/O (UHVIO) * High-Speed I2C and I2C * Enhanced Secure Digital Host Controller (eSDHC) NOTE The term `OVDD' in this section refers to the associated supply rail of an input or output. The association is shown in Table 111.
3.3.1
GPIO/HSGPIO I/0 DC Parameters
Table 13. GPIO/HSGPIO DC Electrical Characteristics
Parameter Symbol Voh Vol Ioh Test Conditions Iout = -1 mA Iout = 1mA Vout = 0.8xOVDD Low drive Medium drive High drive Max drive Vout = 0.2xOVDD Low drive Medium drive High drive Max drive -- -- Min OVDD -0.15 -- -1.9 -3.7 -5.2 -6.6 -- 1.9 3.7 5.2 6.6 0.7 x OVDD 0 -- -- OVDD 0.3xOVDD -- mA Typ -- -- -- Max OVDD + 0.3 0.15 -- mA Unit V V
The parameters in Table 13 are guaranteed per the operating ranges in Table 8, unless otherwise noted.
High-level output voltage Low-level output voltage High-level output current
Low-level output current
Iol
High-Level DC input voltage1 Low-Level DC input voltage1
VIH VIL
V V
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Electrical Characteristics
Table 13. GPIO/HSGPIO DC Electrical Characteristics (continued)
Parameter Input Hysteresis Schmitt trigger VT+ 1, 2 Schmitt trigger VT-1, 2 Symbol VHYS VT+ VTIIN IIN IIN IIN IIN Icc-ovdd Test Conditions OVDD = 1.875 OVDD = 2.775 -- -- VI = OVDD or 0 VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 V I= OVDD VI = 0 VI = OVDD VI = OVDD or 0 OVDD = 1.875V OVDD = 2.775V Min 0.25 0.5OVDD -- -- -- -- -- -- -- -- -- Typ 0.34 0.45 -- -- -- -- -- -- -- -- 22 17 0.5 Max -- -- Unit V V V -- A A A A A k
x OVDD
TBD 161 TBD 76 TBD 36 TBD TBD 36 TBD -- --
Input current (no pull-up/down) Input current (22 k Pull-up) Input current (47 k Pull-up) Input current (100 k Pull-up) Input current (100 k Pull-down) High-impedance I/O supply current Keeper Circuit Resistance
1
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3.3.2
DDR2 I/O DC Parameters
Table 14. DDR2 I/O DC Electrical Parameters
Parameters Symbol Voh Vol Ioh Iol VIH VIL Vin Test Conditions -- -- OVDD=1.7V Vout=1.42V -13.4 OVDD=1.7V Vout=0.28V 13.4 -- -- -- -- Vtt tracking OVDD/2 VI = 0 VI=OVDD Min OVDD - 0.28 -- 0.28 -- -- Max -- Unit V V mA mA V
The parameters in Table 14 are guaranteed per the operating ranges in Table 8, unless otherwise noted.
High-level output voltage Low-level output voltage Output minimum Source Current Output min Sink Current DC input Logic High DC input Logic Low Input voltage range of each differential input
OVDD/2+0.125 OVDD+0.3 -0.3 -0.3 0.25
OVDD/2-0.125 V OVDD+0.3 OVDD+0.6 V V
Differential input voltage required for switching Vid Termination Voltage Input current (no pull-up/down) Vtt Iin
OVDD/2 - 0.04 OVDD/2 + 0.04 V -- -- TBD TBD A
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Electrical Characteristics
3.3.3
Low Voltage I/O (LVIO) DC Parameters
Table 15. LVIO DC Electrical Characteristics
The parameters in Table 15 are guaranteed per the operating ranges in Table 8, unless otherwise noted.
DC Electrical Characteristics High-level output voltage Low-level output voltage High-level output current
Symbol Voh Vol I Ioh
Test Conditions Iout = -1 mA Iout = 1 mA Vout = 0.8 x OVDD Low Drive Medium Drive High Drive Max Drive Vout = 0.2 x OVDD Low Drive Medium Drive High Drive Max Drive -- -- OVDD = 1.875 OVDD = 2.775 -- -- VI = 0 or OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD OVDD = 1.875V OVDD = 2.775V
Min OVDD-0.15 -- -2.1 -4.2 -6.3 -8.4
Typ -- -- --
Max -- 0.15 --
Unit V V
mA
Low-level output current
I Iol
-- 2.1 4.2 6.3 8.4 0.7 x OVDD 0 0.35 0.5 x OVDD -- -- -- -- -- -- -- -- -- -- 0.62 1.27 -- -- -- -- -- -- -- 22 17
-- mA
High-Level DC input voltage1 Low-Level DC input voltage1 Input Hysteresis Schmitt trigger VT+1, 2 Schmitt trigger VT-1, 2 Input current (no pull-up/down) Input current (22 k Pull-up) Input current (47 k Pull-up) Input current (100 k Pull-up) Input current (100 k Pull-down) Keeper Circuit Resistance
1
VIH VIL VHYS VT+ VT- IIN IIN IIN IIN IIN --
OVDD 0.3 x OVDD -- -- 0.5 x OVDD TBD 16 TBD 76 TBD 36 TBD TBD 36 -- --
V V V V V A A A A A k
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
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Electrical Characteristics
3.3.4
Ultra-High Voltage I/O (UHVIO) DC Parameters
Table 16. UHVIO DC Electrical Characteristics1
DC Electrical Characteristics Symbol Voh Vol Ioh_lv Test Conditions Iout = -1mA Iout = 1mA Vout = 0.8 x OVDD Low Drive Medium Drive High Drive Vout = 0.8 x OVDD Low Drive Medium Drive High Drive Vout = 0.2 x OVDD Low Drive Medium Drive High Drive Vout = 0.2 x OVDD Low Drive Medium Drive High Drive -- -- low voltage mode high voltage mode -- -- VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD VI = 0 VI = OVDD NA Min OVDD-0.15 -- -2.2 -4.4 -6.6 -- -5.1 -10.2 -15.3 -- 2.2 4.4 6.6 -- 5.1 10.2 15.3 0.7 x OVDD 0 0.38 0.95 0.5OVDD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 17 OVDD 0.3 x OVDD 0.43 1.33 -- 0.5 x OVDD TBD 202 TBD 61 TBD 47 TBD TBD 5.7 -- -- mA V V V V V A A A A A k -- mA -- mA Typ -- -- -- Max -- 0.15 -- mA Unit V V
The parameters in Table 16 are guaranteed per the operating ranges in Table 8, unless otherwise noted.
High-level output voltage Low-level output voltage High-level output current, low voltage mode
High-level output current, high voltage mode Ioh_hv
Low-level output current, low voltage mode Iol_lv
Low-level output current, high voltage mode Iol_hv
High-Level DC input voltage2,3 Low-Level DC input Input Hysteresis Schmitt trigger VT+2,4 Schmitt trigger VT-2,4 voltage2,3
VIH VIL VHYS VT+ VT- IIN IIN IIN IIN IIN --
Input current (no pull-up/down) Input current (22 k Pull-up) Input current (47 k Pull-up) Input current (100 k Pull-up) Input current (360 k Pull-down) Keeper Circuit Resistance
1 2
This table applies with VCC down to 0.9 V. UHVIO are functional down to 0.85 V with degraded performance. To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.
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Electrical Characteristics
3
Overshoot and undershoot conditions (transitions above OVDD and below OVSS) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3.3.5
I2C I/O DC Parameters
NOTE: See the errata for HS-I2C in i.MX51 Chip Errata document. The two standard I2C modules have no errata The DC Electrical Characteristics listed below are guaranteed using operating ranges per Table 8, unless otherwise noted.
Table 17. I2C Standard/Fast/High-Speed Mode Electrical Parameters for Low/Medium Drive Strength
Parameter Low-level output voltage High-Level DC input voltage Low-Level DC input voltage1 Input Hysteresis Schmitt trigger VT+1,2 Schmitt trigger VT-
1,2 1
Symbol Vol VIH VIL VHYS VT+ VT- Iin
Test Conditions Iol = 3mA -- -- -- -- -- VI = OVDD or 0
Min -- 0.7 x OVDD 0 0.25 0.5 x OVDD -- --
Typ -- -- -- -- -- -- --
Max 0.4 OVDD 0.3 x OVDD -- -- 0.5 x OVDD TBD
Unit V V V V V V A
I/O leakage current (no pull-up)
1
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1ns to 1s. 2 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
3.3.6
eSDHCv2 Electrical I/O DC Parameters
This module is designed to interface with both low and high-voltage cards. See Table 8 for UHVIO supply ranges. Table 18 lists the Module Name electrical DC characteristics.
Table 18. MMC/SD Interface Electrical Specification
Parameter Min Max All Inputs Input Leakage Current -10 10 All Outputs Output Leakage Current -10 10 Power Supply Power Up Time Supply Current -- 100 250 200 ms mA -- -- A -- A -- Unit Condition/Remark
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Electrical Characteristics
Table 18. MMC/SD Interface Electrical Specification (continued)
Parameter Min Max Unit Condition/Remark
Bus Signal Line Load Pull-up Resistance Open Drain Resistance External Loading Drive 10 NA 40 100 NA -- k k pF Internal Pull-up For MMC cards only CMD/CLK/DAT0-7 PADs must drive external 40 pF loading in all working conditions For MMC cards only VDD -0.2 -- -- 0.3 Bus Signal Levels Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage 0.75 x VDD -- 0.625 x OVDD GND -0.3 -- 0.125 x OVDD OVDD + 0.3 0.25 x OVDD V V V V V V
Open Drain Signal Level Output High Voltage Output Low Voltage
IOH = -100 A IOL = 2 mA
IOH = -100 A @VDD min IOL = 100 A @VDD min
-- --
3.3.7 3.3.8
USBOTG Electrical DC Parameters USB Port Electrical DC Characteristics
Table 19. USBOTG Interface Electrical Specification
Parameter Symbol VIH Signals USB_VPOUT USB_VMOUT USB_XRXD, USB_VPIN, USB_VMIN USB_VPOUT USB_VMOUT USB_XRXD, USB_VPIN, USB_VMIN USB_VPOUT USB_VMOUT USB_TXENB USB_VPOUT USB_VMOUT USB_TXENB Min VDD x 0.7 Max VDD Unit V Test Conditions --
Table 19 and Table 20 list the electrical DC characteristics.
Input High Voltage
Input low Voltage
VIL
0
VDD x 0.3
V
--
Output High Voltage
VOH
VDD -0.43
--
V
7 mA Drv at IOH = 5 mA 7 mA Drv at IOH = 5 mA
Output Low Voltage
VOL
--
0.43
V
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Electrical Characteristics
Table 20. USB Interface Electrical Specification
Parameter Input High Voltage Symbol VIH Signals USB_DAT_VP USB_SE0_VM USB_RCV, USB_VP1, USB_VM1 USB_DAT_VP USB_SE0_VM USB_RCV, USB_VP1, USB_VM1 USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_TXOE_B Min VDD x 0.7 VDD Max V Unit Test Conditions --
Input Low Voltage
VIL
0
VDD x 0.3
V
--
Output High Voltage
VOH
VDD -0.43
--
V
7 mA Drv at Iout = 5 mA 7 mA Drv at Iout = 5 mA
Output Low Voltage
VOL
--
0.43
V
3.4
Output Buffer Impedance Characteristics
This section defines the I/O Impedance parameters of the i.MX51A processor.
3.4.1
LVIO I/O Output Buffer Impedance
Table 21. LVIO I/O Output Buffer Impedance
Typical
Parameter
Symbol
Conditions Low Drive Strength, Ztl = 150 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50 Max Drive Strength, Ztl = 37.5 Low Drive Strength, Ztl = 150 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50 Max Drive Strength, Ztl = 37.5
Min OVDD 2.775 V OVDD 1.875 V
Max
Unit
Output Driver Impedance
Rpu
80 40 27 20 64 32 21 16
104 52 35 26 88 44 30 22
150 75 51 38 134 66 44 34
250 125 83 62 243 122 81 61
Output Driver Impedance
Rpd
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3.4.2
DDR Output Buffer Impedance
Table 22. DDR I/O Output Buffer Impedance
Best Case Tj = -20 C OVDD = 1.95 V VCC = 1.3 V s0-s5 000000 Typical Tj = 25 C OVDD = 1.8 V VCC = 1.2 V Worst Case Tj = 105 C OVDD = 1.6 V VCC = 1.1 V s0-s5 111111 90.3 45.4 32 72 36 24.3
Parameter
Symbol
Test Conditions
Unit
s0-s5 s0-s5 s0-s5 111111 101010 111111 55.2 27.6 18.4 32.8 16.4 11 150 75 50 131 65.6 43.8 50.4 34.8 23.2 48.8 22 14.6
Output Driver Impedance Output Driver Impedance
Rpu
Low Drive Strength, Ztl = 150 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50 , Low Drive Strength, Ztl = 150 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50 ,
280 140 93.4 293 147 87.7
Rpd
3.4.3
UHVIO Output Buffer Impedance
Table 23. UHVIO Output Buffer Impedance
Min Typ OVDD 3.3 V 135 67 45 154 77 51 Max OVDD 1.65 V 198 99 66 179 89 60 OVDD 3.6 V 206 103 69 217 109 72 Unit
Parameter
Symbol
Test Conditions
OVDD 1.95 V 98 49 32 97 49 32
OVDD OVDD 3.0 V 1.875 V 114 57 38 118 59 40 124 62 41 126 63 42
Output Driver Impedance Output Driver Impedance
Rpu
Low Drive Strength, Ztl = 150 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50 Low Drive Strength, Ztl =1 50 Medium Drive Strength, Ztl = 75 High Drive Strength, Ztl = 50
Rpd
NOTE Output driver impedance is measured with "long" transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 3).
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Electrical Characteristics
OVDD PMOS (Rpu) Ztl , L = 20 inches ipp_do predriver pad Cload = 1p NMOS (Rpd) OVSS U,(V) Vin (do) VDD
t,(ns) 0 U,(V) Vout (pad) OVDD
Vref1 Vref
Vref2
t,(ns) 0
Rpu =
Vovdd - Vref1 Vref1
x Ztl
Rpd =
Vref2 Vovdd - Vref2
x Ztl
Figure 3. Impedance Matching Load for Measurement
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3.5
I/O AC Parameters
The load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. AC electrical characteristics for slow and fast I/O are presented in the Table 24 and Table 25, respectively.
From Output Under Test Test Point CL CL includes package, probe and fixture capacitance
Figure 4. Load Circuit for Output
NVCC 80% Output (at I/O) tr 20% tf 80% 20% 0V
Figure 5. Output Transition Time Waveform
3.5.1
Slow I/O AC Parameters
Table 24. Slow I/O AC Parameters
Parameter Symbol tr, tf tr, tf tr, tf tr, tf tps tps tps tps tdit tdit tdit Test Condition Min Rise/Fall 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF -- -- -- -- -- -- -- 0.5/0.65 0.32/0.37 0.43/0.54 0.26/0.41 0.34/0.41 0.18/0.2 0.20/0.22 0.09/0.1 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max Rise/Fall 1.98/1.52 3.08/2.69 2.31/1.838 3.8/2.4 2.92/2.43 5.37/4.99 4.93/4.53 10.55/9.79 -- -- -- -- 30 23 15 Unit ns ns ns ns V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns
Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (Max Drive) Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Medium Drive) Output Pad Slew Rate (Low Drive) Output Pad di/dt (Max Drive) Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive)
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Electrical Characteristics
Table 24. Slow I/O AC Parameters (continued)
Parameter Output Pad di/dt (Low drive) Input Transition Times1
1
Symbol tdit trm
Test Condition Min Rise/Fall -- -- -- --
Typ -- --
Max Rise/Fall 7 25
Unit mA/ns ns
Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
3.5.2
Fast I/O AC Parameters
Table 25. Fast I/O AC Parameters
Parameter Symbol tr, tf tr, tf tr, tf tr, tf tps tps tps tps tdit tdit tdit tdit trm Test Condition 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF -- -- -- -- -- Min Rise/Fall -- -- -- -- 0.69/0.78 0.36/0.39 0.55/0.62 0.28/0.30 0.39/0.44 0.19/0.20 0.21/0.22 0.09/0.1 -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max Rise/Fall 1.429/1.275 2.770/2.526 1.793/1.607 3.565/3.29 2.542/2.257 5.252/4.918 4.641/4.456 10.699/10.0 -- -- -- -- 70 53 35 18 25 Unit ns ns ns ns V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns
Output Pad Transition Times (Max Drive) Output Pad Transition Times (High Drive) Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (Max Drive) Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Medium Drive) Output Pad Slew Rate (Low Drive) Output Pad di/dt (Max Drive) Output Pad di/dt (High Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times1
1
Hysteresis mode is recommended for inputs with transition time greater than 25 ns.
3.5.3
I2C AC Parameters
NOTE: See the errata for HS-I2C in i.MX51 Chip Errata document. The two standard I2C modules have no errata Figure 6 depicts the load circuit for output pads for standard- and fast-mode. Figure 7 depicts the output pad transition time definition. Figure 6 depicts pull-up current source measurement for HS-mode. Figure 8
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Electrical Characteristics
depicts load circuit with external pull-up current source for HS-mode. Figure 9 depicts HS-mode timing definition.
From Output Under Test Test Point CL
CL includes package, probe and fixture capacitance
Figure 6. Load Circuit for Standard- and Fast-Mode
OVDD
70% Output 30% tf
0V
Figure 7. Definition of Timing for Standard- and Fast-Mode
OVDD 3 mA1 From Output Under Test Test Point CL2
Notes: 1Load current when output is between 0.3xOVDD and 0.7xOVDD 2CL includes package, probe, and fixture capacitance.
Figure 8. Load Circuit for HS-Mode with External Pull-Up Current Source
OVDD
70% 30% Output (at pad) tTLH
70% 30% 0V tTHL
PA3Max = max of tTLH and tTHL PA4Max = max tTHL
Figure 9. Definition of Timing for HS-Mode
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Electrical Characteristics
The electrical characteristics for I2C I/O are listed in the tables from the Table 26 to the Table 29 on page 33. Characteristics are guaranteed using operating ranges per Table 8, unless otherwise noted.
Table 26. I2C Standard- and Fast-Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 2.7 V-3.3 V
Parameter Output fall time, (low driver strength) Output fall time, (medium driver strength) Symbol tf tf Test Conditions from V IHmin to VILmax with CL from 10 pF to 400 pF from V IHmin to VILmax with CL from 10 pF to 400 pF Min -- -- Typ -- -- Max 52 28 Unit ns ns
Table 27. I2C Standard- and Fast-Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 1.65 V-1.95 V
Parameter Output fall time, (low driver strength) Output fall time, (medium driver strength) Symbol tof tof Test Conditions from V IHmin to VILmax with CL from 10 pF to 400 pF from V IHmin to VILmax with CL from 10 pF to 400 pF Min -- -- Typ -- -- Max 70 35 Unit ns ns
Table 28. I2C High-Speed Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 2.7 V - 3.3 V
Parameter Output rise time (current-source enabled) and fall time at SCLH (low driver strength) Output rise time (current-source enabled) and fall time at SCLH (medium driver strength) Output fall time at SDAH (low driver strength) Output fall time at SDAH (medium driver strength) Output fall time at SDAH (low driver strength) Output fall time at SDAH (medium driver strength) Symbol trCL, tfCL Test Conditions with a 3mA external pull-up current source and CL = 100 pF with a 3mA external pull-up current source and CL = 100 pF with CL from 10 pF to 100 pF with CL from 10 pF to 100 pF CL = 400 pF CL = 400 pF Min -- Typ -- Max 18/21 Unit ns
trCL, tfCL
--
--
9/9
ns
tfDA tfDA tfDA tfDA
-- -- -- --
-- -- -- --
14 8 52 27
ns ns ns ns
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Table 29. I2C High-Speed Mode Electrical Parameters for Low/Medium Drive Strength and OVDD = 1.65 V - 1.95 V
Parameter Output rise time (current-source enabled) and fall time at SCLH (low driver strength) Output rise time (current-source enabled) and fall time at SCLH (medium driver strength) Output fall time at SDAH (low driver strength) Output fall time at SDAH (medium driver strength) Output fall time at SDAH (low driver strength) Output fall time at SDAH (medium driver strength) Symbol trCL, tfCL Test Conditions with a 3mA external pull-up current source and CL = 100 pF with a 3mA external pull-up current source and CL = 100 pF with CL from 10 pF to 100 pF with CL from 10 pF to 100 pF CL = 400 pF CL = 400 pF Min -- Typ -- Max 10/74 Unit ns
trCL, tfCL
--
--
7/14
ns
tfDA tfDA tfDA tfDA
0 0 30 15
-- -- -- --
17 9 67 34
ns ns ns ns
Table 30. Low Voltage I2C I/O Parameters
Parameter Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition
1
Symbol tdit tdit trm
Test Condition Min Rise/Fall -- -- -- -- -- --
Typ -- -- --
Max Rise/Fall 22 11 25
Unit mA/ns mA/ns ns
Times1
Hysteresis mode is recommended for inputs with transition time greater than 25 ns
Table 31. High Voltage I2C I/O Parameters
Parameter Output Pad Transition Times (Medium Drive) Output Pad Transition Times (Low Drive) Output Pad Slew Rate (Medium Drive) Output Pad Slew Rate (Low Drive) Output Pad di/dt (Medium drive) Output Pad di/dt (Low drive) Input Transition Times1
1
Symbol tr, tf tr, tf tps tps tdit tdit trm
Test Condition Min Rise/Fall 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF 15 pF 35 pF -- -- -- -- -- 0/0 0/0 0/0 0/0 -- -- --
Typ -- -- -- -- -- -- --
Max Rise/Fall 3/3 6/5 5/5 9/9 -- -- 36 16 25
Unit ns ns V/ns V/ns mA/ns mA/ns ns
Hysteresis mode is recommended for inputs with transition time > 25 ns
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Electrical Characteristics
3.6
Module Timing
This section contains the timing and electrical parameters for the modules in the i.MX51A processor.
3.6.1
Reset Timings Parameters
Figure 10 shows the reset timing and Table 32 lists the timing parameters.
RESET_IN (Input) CC1
Figure 10. Reset Timing Diagram Table 32. Reset Timing Parameters
ID CC1 Parameter Duration of RESET_IN to be qualified as valid (input slope = 5 ns) Min 50 Max -- Unit ns
3.6.2
WDOG Reset Timing Parameters
Figure 11 shows the WDOG reset timing and Table 33 lists the timing parameters.
WATCHDOG_RST (Input) CC5
Figure 11. WATCHDOG_RST Timing Diagram Table 33. WATCHDOG_RST Timing Parameters
ID CC5 Parameter Duration of WATCHDOG_RESET Assertion Min 1 Max -- Unit TCKIL
NOTE CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 s.
3.6.3
AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is hence governed by the SSI module.
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3.6.4
Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required
Table 34. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter Input frequency VIL (for square wave input) VIH (for square wave input) Sinusoidal input amplitude Output duty cycle
1 2
Min 8.0 0 (VCC 1 -0.25) 0.4 45
2
Typ -- -- -- -- 50
Max 40.0 0.3 3 VDD 55
Unit MHz V V Vp-p %
VCC is the supply voltage of CAMP. This value of the sinusoidal input will be determined during characterization.
3.6.5
DPLL Electrical Parameters
Table 35. DPLL Electrical Parameters
Parameter Test Conditions/Remarks -- -- -- -- -- Should be less than denominator -- -- -- -- (peak value) -- FPL mode, integer and fractional MF Min 10 10 300 1 5 -67108862 1 48.5 -- -- -- -- -- Typ -- -- -- -- -- -- -- 50 -- -- 0.02 2.0 -- Max 100 40 1025 16 15 67108862 67108863 51.5 398 100 0.04 3.5 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) Unit MHz MHz MHz -- -- -- -- % Tdpdref
Reference clock frequency range1 Reference clock frequency range after pre-divider Output clock frequency range (dpdck_2) Pre-division factor2 Multiplication factor integer part Multiplication factor numerator3 Multiplication factor Output Duty Cycle Frequency lock (FOL mode or non-integer MF) Phase lock time Frequency jitter5 time4 denominator2
s
Tdck
ns mW
Phase jitter (peak value) Power dissipation
fdck = 300 MHz @ avdd = 1.8 V, dvdd = 1.2 V fdck = 650 MHz @ avdd = 1.8 V, dvdd = 1.2 V
1 2
Device input range cannot exceed the electrical specifications of the CAMP, see Table 34. The values specified here are internal to DPLL. Inside the DPLL, a "1" is added to the value specified by the user.Therefore, the user has to enter a value "1" less than the desired value at the inputs of DPLL for PDF and MFD.
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Electrical Characteristics
3
The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be zero. 4 Tdpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset. 5 Tdck is the time period of the output clock, dpdck_2.
3.6.6
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among different signals of NFC at the module level in the different operational modes. Timing parameters in Figure 12, through Figure 15, Figure 17, and Table 37 show the default NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B. Timing parameters in Figure 12, Figure 13, Figure 14, Figure 16, Figure 17, and Table 37 show symmetric NFC mode using one Flash clock cycle per one access of RE_B and WE_B. With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20 pF (except for NF16 - 40 pF) and there is max drive strength on all contacts. All timing parameters are a function of T, which is the period of the flash_clk clock ("enfc_clk" at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider. Table 36 demonstrates few examples for clock frequency settings.
Table 36. NFC Clock Settings Examples
emi_slow_clk (MHz) 133 (max value) 133 133
1
nfc_podf (Division Factor) 5 (reset value) 4 3
enfc_clk (MHz) 26.6 33.25 44.33
T--Clock Period (ns)1 38 31 23
Rounded up to whole nanoseconds.
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NFCLE
NF1 NF3
NF2 NF4
NFCE_B NF5 NFWE_B NF8 NFIO[7:0] command NF9
Figure 12. Command Latch Cycle Timing
NF3 NFCE_B NF10 NF11 NF5 NFWE_B NF6 NFALE NF8 NFIO[7:0] Address NF9 NF7 NF4
Figure 13. Address Latch Cycle Timing
NF3 NFCE_B NF10 NF11 NF5 NFWE_B NF8 NFIO[15:0] Data to NF
NF9
Figure 14. Write Data Latch Timing
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Electrical Characteristics
NFCE_B NF14 NF15 NF13 NFRE_B NF16 NFRB_B NF12 NFIO[15:0] Data from NF NF17
Figure 15. Read Data Latch Timing - asymmetric mode.
NFCE_B NF14 NF15 NF13 NFRE_B NF16 NFRB_B NF12 NFIO[15:0] Data from NF NF18
Figure 16. Read Data Latch Timing - Symmetric Mode.
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Electrical Characteristics
NF19
NFCLE NF20 NFCE_B
NFWE_B NF22 NFRE_B
NF21
NFRB_B
Figure 17. Other Timing Parameters. Table 37. NFC--Timing Characteristics
ID NF1 NF2 NF3 NF4 NF5 NF6 NF7 NF8 NF9 NF10 NF11 NF12 NF13 NF14 NF15 NF161 NF173 NF184 NF19 NF20 PARAMETER NFCLE setup Time NFCLE Hold Time NFCE_B Setup Time NFCE_B Hold Time NFWE_B Pulse Width NFALE Setup Time NFALE Hold Time Data Setup Time Data Hold Time Write Cycle Time NFWE_B Hold Time Ready to NFRE_B Low NFRE_B Pulse Width READ Cycle Time NFRE_B High Hold Time Data Setup on READ Data Hold on READ Data Hold on READ CLE to RE delay CE to RE delay Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREH tDSR tDHR tDHR tCLR tCRE Asymmetric Mode Min 2T+0.1 T-4.45 2T+0.95 2T-5.55 T-1.4 2T+0.1 T-4.45 T-0.9 T-5.55 2T T-1.15 9T+8.9 1.5T 2T 0.5T-1.15 11.2+0.5T-Tdl2 0 13T+1.5 T-3.45 Symmetric Mode Min 2T+0.1 T-4.45 T+0.95 1.5T-5.55 0.5T-1.4 2T+0.1 T-4.45 0.5T-0.9 0.5T-5.55 T 0.5T-1.15 9T+8.9 0.5T T 0.5T-1.15 11.2-Tdl2 Tdl2-11.2 13T+1.5 T-3.45 T+0.3 Max 2Taclk+T 2Taclk+T
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Electrical Characteristics
Table 37. NFC--Timing Characteristics (continued)
ID NF21 NF22
1
PARAMETER WE high to RE low WE high to busy
Symbol tWHR tWB
Asymmetric Mode Min 14T-5.45
Symmetric Mode Min 14T-5.45
Max
6T
tDSR is calculated by the following formula: Asymmetric mode: tDSR = tREpd + tDpd + 1/2T - Tdl2 Symmetric mode: tDSR = tREpd + tDpd - Tdl2 tREpd + tDpd = 11.2 ns (including clock skew) where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay from IO pad to EMI including IO pad delay. tDSR can be used to determine tREA max parameter with the following formula: tREA = 1.5T - tDSR. 2 Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (Taclk). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. Taclk is "emi_slow_clk" of the system, which default value is 7.5 ns (133MHz). 3 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max tRHZ value that can be used with NFC. Taclk is "emi_slow_clk" of the system. 4 NF18 is defined only in Symmetric operation mode. Tdl2 - (tREpd + tDpd) tDHR (MIN) is calculated by the following formula: where tREpd is RE propogation delay in the chip including IO pad delay, and tDpd is Data propogation delay from IO pad to EMI including IO pad delay. NF18 max value is equivalent to max tRHZ value that can be used with NFC. Taclk is "emi_slow_clk" of the system.
3.6.7
3.6.7.1
External Interface Module (WEIM)
WEIM Signal Cross Reference
Table 38 is a guide to help the user identify signals in the WEIM Chapter of the Reference Manual Chapter that are the same as those mentioned in this data sheet.
Table 38. WEIM Signal Cross Reference
Reference Manual WEIM Chapter Nomenclature BCLK CSx WE_B OE_B BEy_B ADV ADDR ADDR/M_DATA Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUX Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[27:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode)
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Table 38. WEIM Signal Cross Reference (continued)
Reference Manual WEIM Chapter Nomenclature DATA WAIT_B Data Sheet Nomenclature, Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUX Controller Chapter Nomenclature EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT
3.6.7.2
WEIM Internal Module Multiplexing
Table 39 provides WEIM internal muxing information.
Table 39. WEIM Internal Module Multiplexing
Package Signal Name EIM_DA0 EIM_DA1 EIM_DA2 EIM_DA3 EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_DA10 EIM_DA11 EIM_DA12 EIM_DA13 EIM_DA14 EIM_DA15 EIM_D16 EIM_D17 EIM_D18 EIM_D19 EIM_D20 EIM_D21 EIM 16-Bit MUXed Data/Address DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 -- -- -- -- -- -- EIM 16-Bit Non-MUXed Data/Address A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 EIM 32-Bit MUXed Data/Address DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 DA8 DA9 DA10 DA11 DA12 DA13 DA14 DA15 D16 D17 D18 D19 D20 D21 EIM MUXed to NAND Flash DATA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
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Electrical Characteristics
Table 39. WEIM Internal Module Multiplexing (continued)
Package Signal Name EIM_D22 EIM_D23 EIM_D24 EIM_D25 EIM_D26 EIM_D27 EIM_D28 EIM_D29 EIM_D30 EIM_D31 EIM_A16 EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A22 EIM_A23 EIM_A24 EIM_A25 EIM_A26 EIM_A27 EIM_EB0 EIM_EB1 EIM_EB2 EIM_EB3 EIM_OE EIM_CS0 EIM_CS1 EIM_CS2 EIM_CS3 EIM 16-Bit MUXed Data/Address -- -- -- -- -- -- -- -- -- -- A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 EB0 EB1 EB2 EB3 OE CS0 CS1 CS2 CS3 EIM 16-Bit Non-MUXed Data/Address D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 EB0 EB1 EB2 EB3 OE CS0 CS1 CS2 CS3 EIM 32-Bit MUXed Data/Address D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 EB0 EB1 EB2 EB3 OE CS0 CS1 CS2 CS3 EIM MUXed to NAND Flash DATA -- -- -- -- -- -- -- -- -- -- A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 EB0 EB1 EB2 EB3 OE CS0 CS1 CS2 CS3
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Electrical Characteristics
Table 39. WEIM Internal Module Multiplexing (continued)
Package Signal Name EIM_CS4 EIM_CS5 EIM_DTACK EIM_WAIT EIM_LBA EIM_BCLK EIM_RW EIM_CRE EIM_SDBA1 EIM_SDBA0 EIM 16-Bit MUXed Data/Address CS4 CS5 DTACK WAIT LBA BCLK RW CRE SDBA1 SDBA0 EIM 16-Bit Non-MUXed Data/Address CS4 CS5 DTACK WAIT LBA BCLK RW CRE SDBA1 SDBA0 EIM 32-Bit MUXed Data/Address CS4 CS5 DTACK WAIT LBA BCLK RW CRE SDBA1 SDBA0 EIM MUXed to NAND Flash DATA CS4 CS5 DTACK WAIT LBA BCLK RW CRE SDBA1 SDBA0
3.6.7.3
General WEIM Timing
The following diagrams and tables specify the timings related to the WEIM module. All WEIM output control signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields.
,
WE1
BCLK
WE2
...
WE3 WE5 WE7 WE9
WE4
Address
WE6
CSx_B
WE8
WE_B
WE10
OE_B
WE11
WE12
BEy_B
WE13
WE14
ADV_B
WE15 WE17
WE16
Output Data
Figure 18. WEIM Outputs Timing Diagram
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Electrical Characteristics
BCLK
WE18
Input Data
WE19 WE20
WAIT_B
WE21
Figure 19. WEIM Inputs Timing Diagram Table 40. WEIM Bus Timing Parameters 1
BCD = 0 ID Parameter Min WE1 WE2 WE3 WE4 WE5 WE6 WE7 WE8 WE9 WE10 WE11 WE12 WE13 WE14 WE15 WE16 WE17 WE18 WE19 BCLK Cycle time2 BCLK Low Level Width BCLK High Level Width Clock rise to address valid3 Clock rise to address invalid Clock rise to CSx_B valid Clock rise to CSx_B invalid Clock rise to WE_B Valid Clock rise to WE_B Invalid Clock rise to OE_B Valid Clock rise to OE_B Invalid Clock rise to BEy_B Valid Clock rise to BEy_B Invalid Clock rise to ADV_B Valid Clock rise to ADV_B Invalid Clock rise to Output Data Valid Clock rise to Output Data Invalid Input Data setup time to Clock rise Input Data hold time from Clock rise t 0.4t 0.4t 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 0.5t-1.25 2 2.5 Max -- -- -- 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 0.5t+1.75 -- -- Min 2t 0.8t 0.8t t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 t-1.25 2 2.5 Max -- -- -- t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 t+1.75 -- -- Min 3t 1.2t 1.2t 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2t-1.25 2 2.5 Max -- -- -- 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 2t+1.75 -- -- Min 4t 1.6t 1.6t 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 3t-1.25 2t-1.25 2t-1.25 2 2.5 Max -- -- -- 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 3t+1.75 2t+1.75 2t+1.75 -- -- BCD = 1 BCD = 2 BCD = 3
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Electrical Characteristics
Table 40. WEIM Bus Timing Parameters (continued)1
BCD = 0 ID Parameter Min WE20 WE21
1
BCD = 1 Min 2 2.5 Max -- --
BCD = 2 Min 2 2.5 Max -- --
BCD = 3 Min 2 2.5 Max -- --
Max -- --
WAIT_B setup time to Clock rise WAIT_B hold time from Clock rise
2 2.5
t is axi_clk cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency is 104 MHz. As a result if BCD = 0, axi_clk must be 104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to WEIM is decreased to 104 MHz, other busses are impacted which are clocked from this source. See the CCM chapter of the i.MX51 Reference Manual for a detailed clock tree description. 2 BCLK parameters are being measured from the 50% point. i.e., high is defined as 50% of signal value and low is defined as 50% as signal value. 3 For signal measurements "High" is defined as 80% of signal value and "Low" is defined as 20% of signal value.
3.6.7.4
Examples of WEIM Accesses
The following diagrams give few examples of basic WEIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings.
BCLK WE4 ADDR CSx_B WE_B WE14 ADV_B WE10 OE_B WE12 BEy_B WE18 DATA D(v1) WE19 WE13 WE11 WE15 Last Valid Address WE6 Address v1 WE5 Next Address WE7
Figure 20. Synchronous Memory Read Access, WSC=1
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Electrical Characteristics
BCLK WE4 ADDR CSx_B WE8 WE_B WE14 ADV_B OE_B WE12 BEy_B WE16 DATA D(V1) WE17 WE13 WE15 WE9 Last Valid Address WE6 WE5 Address V1 WE7 Next Address
Figure 21. Synchronous Memory, Write Access, WSC=1, WBEA=1, WBEN=1, and WADVN=0
BCLK ADDR CSx_B WE_B WE14 ADV_B WE10 OE_B WE12 BEy_B WE21 WAIT_B WE20 WE19 DATA WE18 D(V1) D(V1+1) Halfword Halfword D(V2) D(V2+1) HalfwordHalfword WE13 WE11 WE4 Last Valid Addr WE6 WE5 Address V1 Address V2 WE7
WE15 WE14
WE15
Figure 22. Synchronous 16-Bit Memory, Two Non-Sequential 32-bit Read Accesses, WSC=2, SRD=1, BCD=0
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Electrical Characteristics
BCLK WE4 ADDR CSx_B WE8 WE_B WE14 ADV_B OE_B WE12 BEy_B WE21 WAIT_B WE20 WE17 DATA D(V1) WE16 WE16 WE17 D(V2) D(V3) D(V4) WE13 WE15 WE9 Last Valid Addr WE6 Address V1 WE7 WE5
Figure 23. Synchronous Memory, Burst Write, BCS=1, WSC=4, SRD=1, and BCD=0
BCLK WE4 ADDR/ M_DATA CSx_B WE8 WE_B ADV_B OE_B WE10 BEy_B WE11 WE14 WE15 WE9 LastValid Addr WE6 WE5 Address V1 WE16 Write Data WE7 WE17
Figure 24. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=1, ADVN=1, and ADH=1
NOTE In 32-bit muxed address/data (A/D) mode the16 MSBs are driven on the data bus.
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Electrical Characteristics
BCLK WE4 ADDR/ M_DATA CSx_B WE7 WE_B WE14 ADV_B WE10 OE_B WE12 BEy_B WE13 WE11 WE15 Last Valid Addr WE6 Address V1 WE18 WE5 WE19 Data
Figure 25. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, OEA=2
The Figure 26, Figure 27, Figure 28, and Table 41 help to determine timing parameters relative chip select (CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above.
CSx_B WE31 ADDR WE_B WE39 ADV_B WE35 OE_B WE37 BEy_B DATA WE43 D(V1) WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address
Figure 26. Asynchronous Memory Read Access
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Electrical Characteristics
CSx_B WE31 ADDR WE_B WE39 ADV_B OE_B WE45 BEy_B WE42 DATA WE41 D(V1) WE46 WE40 Last Valid Address WE33 Address V1 WE34 WE32 Next Address
Figure 27. Asynchronous Memory Write Access
CSx_B WE31 ADDR WE_B WE39 ADV_B WE35 OE_B WE37 BEy_B DATA WE43 WE48 DATA WE47 D(V1) WE38 WE44 WE36 WE40 Last Valid Address Address V1 WE32 Next Address
Figure 28. DTACK Read Access Table 41. WEIM Asynchronous Timing Parameters Table Relative Chip Select
Determination by Synchronous Measured Parameters 1 WE4 - WE6 - CSA2 WE7 - WE5 - CSN 3 WE8 - WE6 + (WEA - CSA)
ID
Parameter
Min
Max
Unit
WE31
CSx_B valid to Address Valid
-- -- --
3 - CSA 3 - CSN 3 + (WEA - CSA)
ns ns ns
WE32 Address Invalid to CSx_B invalid WE33 CSx_B Valid to WE_B Valid
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Electrical Characteristics
Table 41. WEIM Asynchronous Timing Parameters Table Relative Chip Select (continued)
Determination by Synchronous Measured Parameters 1 WE7 - WE9 + (WEN - CSN) WE10 - WE6 + (OEA - CSA) WE7 - WE11 + (OEN - CSN) WE12 - WE6 + (RBEA - CSA)
ID
Parameter
Min
Max
Unit
WE34 WE_B Invalid to CSx_B Invalid WE35 CSx_B Valid to OE_B Valid WE36 OE_B Invalid to CSx_B Invalid WE37 CSx_B Valid to BEy_B Valid (Read access)
-- -- -- -- -- -- -- -- -- MAXCO 6 + MAXDI7 0 -- -- MAXCO6 + MAXDTI8 0
3 - (WEN_CSN) 3 + (OEA - CSA) 3 - (OEN - CSN) 3+ (RBEA4 - CSA)
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WE38 BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (RBEN - CSN) (Read access) WE39 CSx_B Valid to ADV_B Valid WE14 - WE6 + (ADV - CSA)
3 - (RBEN5 - CSN) 3 + (ADVA - CSA) 3 - CSN 3 - WCSA 3 - CSN -- -- 3 + (WBEA - CSA) -3 + (WBEN - CSN) -- --
WE40 ADV_B Invalid to CSx_B Invalid WE7 - WE15 - CSN (ADVL is asserted) WE41 CSx_B Valid to Output Data Valid WE42 Output Data Invalid to CSx_B Invalid WE43 Input Data Valid to CSx_B Invalid WE44 CSx_B Invalid to Input Data invalid WE45 CSx_B Valid to BEy_B Valid (Write access) WE16 - WE6 - WCSA WE17 - WE7 - CSN MAXCO + MAXDI 0 WE12 - WE6 + (WBEA - CSA)
WE46 BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (WBEN - CSN) (Write access) WE47 Dtack Valid to CSx_B Invalid WE48 CSx_B Invalid to Dtack invalid
1 2 3 4 5 6 7 8
MAXCO + MAXDTI 0
Parameters WE4... WE21 value see in the Table 41. CS Assertion. This bit field determines when CS signal is asserted during read/write cycles. CS Negation. This bit field determines when CS signal is negated during read/write cycles. BE Assertion. This bit field determines when BE signal is asserted during read cycles. BE Negation. This bit field determines when BE signal is negated during read cycles. Output maximum delay from internal driving the FFs to chip outputs. The Max. delay between all memory controls (addr, csx_b, oe_b, we_b, bey_b, and adv_b) Maximum delay from chip input data to internal FFs. The max. delay between all data input pins. DTACK maximum delay from chip input data to internal FF.
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Electrical Characteristics
3.6.8
3.6.8.1
SDRAM Controller Timing Parameters
Mobile DDR SDRAM Timing Parameters
DD1
SDCLK SDCLK
DD4
CS
DD2 DD3
DD5
RAS
DD5 DD4
CAS
DD4 DD5
WE
DD5
DD6
ADDR ROW/BA
DD7
COL/BA
Figure 29. Mobile DDR SDRAM Basic Timing Parameters Table 42. Mobile DDR SDRAM Timing Parameter Table
200 MHz ID Parameter Symbol Min DD1 DD2 DD3 DD4 DD5 DD6 DD7
1
166 MHz Min 0.45 0.45 6 1.1 1.1 1.1 1.1 Max 0.55 0.55 -- -- -- -- --
133 MHz Unit Min 0.45 0.45 7.5 1.3 1.3 1.3 1.3 Max 0.55 0.55 -- -- -- -- -- tCK tCK ns ns ns ns ns
Max 0.55 0.55 -- -- -- -- --
SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, CKE, WE setup time CS, RAS, CAS, CKE, WE hold time Address output setup time Address output hold time
tCH tCL tCK tIS1 tIH1 tIS1 tIH1
0.45 0.45 5 0.9 0.9 0.9 0.9
This parameter is affected by pad timing. if the slew rate is < 1 V/ns, 0.2 ns should be added to the value. For cmos65 pads this is true for medium and low drive strengths.
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Electrical Characteristics
SDCLK SDCLK_B DD21 DQS (output) DD17 DQ (output) Data DD18 Data DD17 DD18 Data Data Data Data Data Data DD22 DD23
DD19
DD20
DQM (output) DD17
DM
DM DD18
DM DD17
DM
DM DD18
DM
DM
DM
Figure 30. Mobile DDR SDRAM Write cycle Timing Diagram Table 43. Mobile DDR SDRAM Write Cycle Parameter Table1
200 MHz2 ID Parameter Symbol Min DD17 DD18 DD19 DD20 DD21 DD22 DD23
1
166 MHz Min 0.6 0.6 0.2 0.2 0.75 0.4 0.4 Max -- -- -- -- 1.25 0.6 0.6
133 MHz Unit Min 0.8 0.8 0.2 0.2 0.75 0.4 0.4 Max -- -- -- -- 1.25 0.6 0.6 ns ns tCK tCK tCK tCK tCK
Max -- -- -- -- 1.25 0.6 0.6
DQ and DQM setup time to DQS DQ and DQM hold time to DQS Write cycle DQS falling edge to SDCLK output setup time Write cycle DQS falling edge to SDCLK output hold time Write command to first DQS latching transition DQS high level width DQS low level width
tDS3 tDH1 tDSS tDSH tDQSS tDQSH tDQSL
0.48 0.48 0.2 0.2 0.75 0.4 0.4
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls 2 SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). 3 This parameter is affected by pad timing. If the slew rate is < 1 V/ns, 0.1 ns should be increased to this value.
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Electrical Characteristics
SDCLK
SDCLK_B DD26 DQS (input) DD25 DD24 DQ (input) Data Data Data Data Data Data Data Data
Figure 31. Mobile DDR SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram Table 44. Mobile DDR SDRAM Read Cycle Parameter Table1
200 MHz2 ID PARAMETER Symbol Min Max Min Max Min Max DD24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS) DD25 DQS DQ in HOLD time from DQS DD26 DQS output access time from SDCLK posedge
1
166 MHz
133 MHz Unit
tDQSQ tQH tDQSCK
-- 1.75 2
0.4 -- 5
-- 2.05 2
0.75 -- 5.5
-- 2.6 2
0.85 -- 6.5
ns ns ns
Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls 2 SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock)
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Electrical Characteristics
3.6.9
DDR2 SDRAM Specific Parameters
Figure 32 shows the timing parameters for DDR2. The timing parameters for this diagram appear in Table 45.
DDR1 SDCLK SDCLK DDR2 DDR4 DDR3 CS
DDR5 RAS
DDR5 DDR4 CAS DDR4 DDR5 WE
DDR5
ODT/CKE DDR6 DDR7 ADDR ROW/BA COL/BA DDR4
Figure 32. DDR2 SDRAM Basic Timing Parameters Table 45. DDR2 SDRAM Timing Parameter Table
SDCLK = 200 MHz ID Parameter Symbol Min DDR1 DDR2 DDR3 DDR4 DDR5 SDRAM clock high-level width SDRAM clock low-level width SDRAM clock cycle time CS, RAS, CAS, CKE, WE, ODT setup time CS, RAS, CAS, CKE, WE, ODT hold time tCH tCL tCK tIS1 tIH1 0.45 0.45 5 0.35 0.475 Max 0.55 0.55 -- -- -- tCK tCK ns ns ns Unit
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Electrical Characteristics
Table 45. DDR2 SDRAM Timing Parameter Table (continued)
SDCLK = 200 MHz ID Parameter Symbol Min DDR6 DDR7
1
Unit Max -- -- ns ns
Address output setup time Address output hold time
tIS1 tIH1
0.35 0.475
These values are for command/address slew rates of 1V/ns and SDCLK / SDCLK_B differential slew rate of 2 V/ns. For different values use the settings shown in Table 46.
Table 46. Derating Values for DDR2-400 (SDCLK = 200 MHz)
Command / Address Slew Rate (V/ns) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.25 0.2 0.15 0.1
1
SDCLK Differential Slew Rates1,2 2.0 V/ns 1.5 V/ns 1.0 V/ns Unit
tlS
+187 +179 +167 +150 +125 +83 +0 -11 -25 -43 -67 -110 -175 -285 -350 -525 -800 -1450
tlH
+94 +89 +83 +75 +45 +21 +0 -14 -31 -54 -83 -125 -188 -292 -375 -500 -708 -1125
tlS
+217 +209 +197 +180 +155 +113 +30 +19 +5 -13 -37 -80 -145 -255 -320 -495 -770 -1420
tlH
+124 +119 +113 +105 +75 +51 +30 +16 -1 -24 -53 -95 -158 -262 -345 -470 -678 -1095
tlS
+247 +239 +227 +210 +185 +143 +60 +49 +35 +17 -7 -50 -115 -225 -290 -465 -740 -1390
tlH
+154 +149 +143 +135 +105 +81 +60 +46 +29 +6 -23 -65 -128 -232 -315 -440 -648 -1065 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Test conditions are: Capacitance 15 pF for DDR contacts. Recommended drive strengths: Medium for SDCLK and High for address and controls. 2 SDCLK and DQS related parameters are measured from the 50% point. For example, a high is defined as 50% of the signal value and a low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK_B
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Electrical Characteristics
SDCLK
SDCLK_B DDR21 DQS (output) DDR18 DDR17 DQ (output) Data Data DDR17 Data Data DDR22 DDR23 DDR18 Data Data Data Data DDR19 DDR20
DQM (output) DDR17
DM
DM DDR18
DM DDR17
DM
DM DDR18
DM
DM
DM
Figure 33. DDR2 SDRAM Write Cycle Table 47. DDR2 SDRAM Write Cycle
SDCLK = 200 MHz ID PARAMETER DQ and DQM setup time to DQS (differential strobe)1 DQ and DQM hold time to DQS (differential strobe)
1
Symbol Min Max -- -- -- -- -- -- 0.25 -- --
Unit
DDR17 DDR18 DDR17 DDR18 DDR19 DDR20 DDR21 DDR22 DDR23
1
tDS(base) tDH(base) tDS1(base)
2
0.15 0.275 0.025 0.025 0.2 0.2 -0.25 0.35 0.35
ns ns ns ns tCK tCK tCK tCK tCK
DQ and DQM setup time to DQS (single-ended strobe)2 DQ and DQM hold time to DQS (single-ended strobe)
tDH1(base) tDSS tDSH tDQSS tDQSH tDQSL
Write cycle DQS falling edge to SDCLK output setup time Write cycle DQS falling edge to SDCLK output hold time DQS latching rising transitions to associated clock edges DQS high level width DQS low level width
These values are for DQ/DM slew rates of 1 V/ns and DQS/DQS_B differential slew rates of 2 V/ns. For different values use derating table below 2 These values are for DQ/DM slew rates of 1 V/ns and DQS slew rates of 1 V/ns. For different values use derating table below
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Electrical Characteristics
Table 48. Derating values for DDR2 Differential DQS1,2
Table 49. Derating values for DDR2 Single Ended DQS3,4
1. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls. 2. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock). 3. Test conditions are: Capacitance 15 pF for DDR PADS. Recommended drive strengths is medium for SDCLK and high for address and controls. 4. SDRAM CLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK (inverted clock).
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Electrical Characteristics
SDCLK SDCLK_B DQS (input)
DDR25 DDR24 DDR26
DQ (input)
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
Figure 34. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Table 50. DDR2 SDRAM Read Cycle1
SDCLK = 200 MHz2 ID Parameter Symbol Min DDR24 DDR25 DDR26
1
Unit Max 0.35 -- 0.5 ns ns ns
DQS - DQ Skew (defines the Data valid window in read cycles related to DQS). DQS DQ in HOLD time from DQS DQS output access time from SDCLK posedge
tDQSQ tQH tDQSCK
-- 1.8 -0.5
Test conditions are: Capacitance of 15 pF for DDR contacts. The recommended drive strength is Medium for SDCLK and High for address and controls 2 SDCLK and DQS related parameters are being measured from the 50% point. that is, high is defined as 50% of signal value and low is defined as 50% as signal value. DDR SDRAM CLK parameters are measured at the crossing point of SDCLK and SDCLK_B.
3.7
3.7.1
External Peripheral Interfaces
CSPI Timing Parameters
This section describes the timing parameters of the CSPI. The CSPI has separate timing parameters for master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these signals is shown in Table 51 on page 59.
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Electrical Characteristics
Table 51. CSPI Nomenclature and Routing
Module eCSPI1 eCSPI2 CSPI
1
I/O Access CSPI11, USBH1, and DI1 via IOMUX NANDF and USBH1 via IOMUX NANDF, USBH1, SD1, SD2, and GPIO via IOMUX
This set of BGA contacts is labeled CSPI, but is actually an eCSPI channel
3.7.1.1
CSPI Master Mode Timing
Figure 35 depicts the timing of CSPI in Master mode and Table 52 lists the CSPI Master Mode timing characteristics.
CSPIx_DRYN1 CS11 CSPIx_CS_x CS1 CS3 CS2 CS2 CS6 CS4 CSPIx_CLK CS7 CS8 CSPIx_DO CS9 CS10 CSPIx_DI CS3 CS5
Figure 35. CSPI Master Mode Timing Diagram Table 52. CSPI Master Mode Timing Parameters
ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 Parameter CSPIx_CLK Cycle Time CSPIx_CLK High or Low Time CSPIx_CLK Rise or Fall CSPIx_CS_x pulse width CSPIx_CS_x Lead Time (CS setup time) CSPIx_CS_x Lag Time (CS hold time) CSPIx_DO Setup Time CSPIx_DO Hold Time CSPIx_DI Setup Time Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso Min 60 6 -- 15 5 5 5 5 5 Max -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
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Electrical Characteristics
Table 52. CSPI Master Mode Timing Parameters (continued)
ID CS10 CS11 CSPIx_DI Hold Time CSPIx_DRYN Setup Time Parameter Symbol tHmiso tSDRY Min 5 5 Max -- -- Unit ns ns
3.7.1.2
CSPI Slave Mode Timing
Figure 36 depicts the timing of CSPI in Slave mode. Table 53 lists the CSPI Slave Mode timing characteristics.
CSPIx_CS_x
CS1
CS3 CS2
CS2
CS6 CS4
CS5
CSPIx_CLK CS9CS10 CSPIx_DI CS7 CS8 CSPIx_DO CS3
Figure 36. CSPI Slave Mode Timing Diagram Table 53. CSPI Slave Mode Timing Parameters
ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 Parameter CSPIx_CLK Cycle Time CSPIx_CLK High or Low Time CSPIx_CLK Rise or Fall CSPIx_CS_x pulse width CSPIx_CS_x Lead Time (CS setup time) CSPIx_CS_x Lag Time (CS hold time) CSPIx_DO Setup Time CSPIx_DO Hold Time CSPIx_DI Setup Time CSPIx_DI Hold Time Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso tHmiso Min 60 15 -- 30 5 5 5 5 5 5 Max -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
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3.7.2
eCSPI Timing Parameters
This section describes the timing parameters of the eCSPI. The eCSPI has separate timing parameters for master and slave modes. The nomenclature used with the CSPI modules and the respective routing of these signals is shown in Table 51 on page 59.
3.7.2.1
eCSPI Master Mode Timing
Figure 35 depicts the timing of eCSPI in Master mode and Table 52 lists the eCSPI Master Mode timing characteristics.
eCSPIx_DRYN1 CS11 eCSPIx_CS_x CS1 CS3 CS2 CS2 CS6 CS4 eCSPIx_CLK CS7 CS8 eCSPIx_DO CS9 CS10 eCSPIx_DI CS3 CS5
Figure 37. eCSPI Master Mode Timing Diagram Table 54. eCSPI Master Mode Timing Parameters
ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 CS11 Parameter eCSPIx_CLK Cycle Time-Read eCSPIx_CLK Cycle Time-Write eCSPIx_CLK High or Low Time eCSPIx_CLK Rise or Fall eCSPIx_CS_x pulse width eCSPIx_CS_x Lead Time (CS setup time) eCSPIx_CS_x Lag Time (CS hold time) eCSPIx_DO Setup Time eCSPIx_DO Hold Time eCSPIx_DI Setup Time eCSPIx_DI Hold Time eCSPIx_DRYN Setup Time Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso tHmiso tSDRY Min 60 15 6 -- 15 5 5 5 5 5 5 5 Max -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
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3.7.2.2
eCSPI Slave Mode Timing
Figure 37 depicts the timing of eCSPI in Slave mode and Table 54 lists the eCSPI Slave Mode timing characteristics.
eCSPIx_CS_x
CS1
CS3 CS2
CS2
CS6 CS4
CS5
eCSPIx_CLK CS9CS10 eCSPIx_DI CS7 CS8 eCSPIx_DO CS3
Figure 38. eCSPI Slave Mode Timing Diagram Table 55. eCSPI Slave Mode Timing Parameters
ID CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 Parameter eCSPIx_CLK Cycle Time-Read eCSPIx_CLK Cycle Time-Write eCSPIx_CLK High or Low Time eCSPIx_CLK Rise or Fall eCSPIx_CS_x pulse width eCSPIx_CS_x Lead Time (CS setup time) eCSPIx_CS_x Lag Time (CS hold time) eCSPIx_DO Setup Time eCSPIx_DO Hold Time eCSPIx_DI Setup Time eCSPIx_DI Hold Time Symbol tclk tSW tRISE/FALL tCSLH tSCS tHCS tSmosi tHmosi tSmiso tHmiso Min 60 15 6 -- 15 5 5 5 5 5 5 Max -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
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3.7.3
eSDHCv2 Timing Parameters
This section describes the electrical information of the eSDHCv2. Figure 39 depicts the timing of eSDHCv2, and Table 56 lists the eSDHCv2 timing characteristics.
SD4 SD2 SD5 SD1
MMCx_CLK SD3 MMCx_CMD MMCx_DAT_0 MMCx_DAT_1 output from eSDHCv2 to card ...... MMCx_DAT_7 MMCx_CMD MMCx_DAT_0 MMCx_DAT_1 input from card to eSDHCv2 ...... MMCx_DAT_3 SD6
SD7
SD8
Figure 39. eSDHCv2 Timing Table 56. eSDHCv2 Interface Timing Specification
ID Parameter Card Input Clock SD1 Clock Frequency (Low Speed) Clock Frequency (SD/SDIO Full Speed/High Speed) Clock Frequency (MMC Full Speed/High Speed) Clock Frequency (Identification Mode) SD2 SD3 SD4 SD5 Clock Low Time Clock High Time Clock Rise Time Clock Fall Time fPP1 fPP2 fPP3 fOD tWL tWH tTLH tTHL 0 0 0 100 7 7 -- -- 400 25/50 20/52 400 -- -- 3 3 kHz MHz MHz kHz ns ns ns ns Symbols Min Max Unit
eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 eSDHC Output Delay tOD -3 3 ns
eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)
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Table 56. eSDHCv2 Interface Timing Specification (continued)
ID SD7 SD8
1 2
Parameter eSDHC Input Setup Time eSDHC Input Hold Time
Symbols tISU tIH4
Min 2.5 2.5
Max -- --
Unit ns ns
In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. In normal speed mode for SD/SDIO card, clock frequency can be any value between 0-25 MHz. In high-speed mode, clock frequency can be any value between 0-50 MHz. 3 In normal speed mode for MMC card, clock frequency can be any value between 0-20 MHz. In high-speed mode, clock frequency can be any value between 0-52 MHz. 4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
3.7.4
FEC AC Timing Parameters
This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps-only 7-wire interface, which uses 7 of the MII pins, for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, refer to the i.MX51 Reference Manual. This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V.
3.7.4.1
MII Receive Signal Timing
The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must exceed twice the FEC_RX_CLK frequency. Table 57 lists the MII receive channel signal timing parameters and Figure 40 shows MII receive signal timings.
.
Table 57. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic1 FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold FEC_RX_CLK pulse width high FEC_RX_CLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FEC_RX_CLK period FEC_RX_CLK period
1
FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.
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M3
FEC_RX_CLK (input)
M4 FEC_RXD[3:0] (inputs) FEC_RX_DV FEC_RX_ER M1 M2
Figure 40. MII Receive Signal Timing Diagram
3.7.4.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency. Table 58 lists MII transmit channel timing parameters and Figure 41 shows MII transmit signal timing diagram for the values listed in Table 58.
Table 58. MII Transmit Signal Timing
Num M5 M6 M7 M8
1
Characteristic1 FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid FEC_TX_CLK pulse width high FEC_TX_CLK pulse width low
Min 5 -- 35% 35%
Max -- 20 65% 65%
Unit ns ns FEC_TX_CLK period FEC_TX_CLK period
FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
.
M7
FEC_TX_CLK (input) M5 M8 FEC_TXD[3:0] (outputs) FEC_TX_EN FEC_TX_ER M6
Figure 41. MII Transmit Signal Timing Diagram
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3.7.4.3
MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)
Table 59 lists MII asynchronous inputs signal timing information. Figure 42 shows MII asynchronous input timings listed in Table 59.
Table 59. MII Async Inputs Signal Timing
Num M91
1
Characteristic FEC_CRS to FEC_COL minimum pulse width
Min 1.5
Max --
Unit FEC_TX_CLK period
FEC_COL has the same timing in 10 Mbit 7-wire interface mode.
.
FEC_CRS, FEC_COL M9
Figure 42. MII Async Inputs Timing Diagram
3.7.4.4
MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
Table 60 lists MII serial management channel timings. Figure 43 shows MII serial management channel timings listed in Table 60. The MDC frequency should be equal to or less than 2.5 MHz to be compliant with the IEEE 802.3 MII specification. However the FEC can function correctly with a maximum MDC frequency of 15 MHz.
Table 60. MII Transmit Signal Timing
ID M10 M11 M12 M13 M14 M15 Characteristic FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay) FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay) FEC_MDIO (input) to FEC_MDC rising edge setup FEC_MDIO (input) to FEC_MDC rising edge hold FEC_MDC pulse width high FEC_MDC pulse width low Min Max 0 -- 18 0 -- 5 -- -- Unit ns ns ns ns
40% 60% FEC_MDC period 40% 60% FEC_MDC period
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M14 M15 FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12
M13
Figure 43. MII Serial Management Channel Timing Diagram
3.7.5
Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)
The FPM is a DPLL that converts a signal operating in the kilohertz region into a clock signal operating in the megahertz region. The output of the FPM provides the reference frequency for the on-chip DPLLs. Parameters of the FPM are listed in Table 61.
Table 61. FPM Specifications
Parameter Reference clock frequency range--CKIL FPM output clock frequency range FPM multiplication factor (test condition is changed by a factor of 2) Lock-in time1 Min 32 8 128 -- -- Typ 32.768 -- -- -- 8 Max 256 33 1024 312.5 20 Unit kHz MHz --
s
ns
Cycle-to-cycle frequency jitter (peak to peak)
1
plrf = 1 cycle assumed missed + x cycles for reset deassert + y cycles for calibration and lock x[ts] = {2,3,5,9}; y[ts] = {7,8,10,14}; where ts is the chosen time scale of the reference clock. In this case reference clock = 32 kHz which makes ts = 0, therefore total time required for achieving lock is 10(1+2+7) cycles or 312.5 s.
3.7.6
High-Speed I2C (HS-I2C) Timing Parameters
This section describes the timing parameters of the HS-I2C module. This module can operate in the following modes: Standard, Fast and High speed. NOTE See the errata for two standard I2C modules that have no errata. the HS-I2C module in the i.MX51 Chip Errata. There are
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3.7.6.1
Standard and Fast Mode Timing Parameters
Figure 44 depicts the standard and fast mode timings of HS-I2C module, and Table 62 lists the timing characteristics.
IC10 IC11 IC9
SDAH IC2 IC8
SCLH
IC4
IC7
IC3
START
IC10 IC6 IC1 IC5
IC11
START
STOP
START
Figure 44. HS-I2C Standard and Fast Mode Bus Timing Table 62. HS-I2C Timing Parameters--Standard and Fast Mode
Standard Mode ID Parameter Min IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12
1
Fast Mode Unit Min 2.5 0.6 0.6 01 0.6 1.3 0.6 1003 1.3 20+0.1Cb4 20+0.1Cb --
4
Max -- -- -- 3.452 -- -- -- -- -- 1000 300 100
Max -- -- -- 0.92 -- -- -- -- -- 300 300 100
SCLH cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of SCLH Clock LOW Period of the SCLH Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both SDAH and SCLH signals Fall time of both SDAH and SCLH signals Capacitive load for each bus line (C b)
10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 -- -- --
s s s s s s s
ns
s
ns ns pF
A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the falling edge of SCLH. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC6) of the SCLH signal 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC8) of 250 ns must then be met. This automatically is the case if the device does not stretch the LOW period of the SCLH signal. If such a device does stretch the LOW period of the SCLH signal, it must output the next data bit to the SDAH line max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCLH line is released. 4 C = total capacitance of one bus line in pF. b
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3.7.6.2
High-Speed Mode Timing Parameters
Figure 45 depicts the high-speed mode timings of HS-I2C module, and Table 63 lists the timing characteristics.
SDAH IC11 IC12
SCLH
IC3
IC6
IC7
IC2 IC13
START
IC9 IC4 IC1 IC5
IC10 IC8
START
STOP
START
Figure 45. High-Speed Mode Timing Table 63. HS-I2C High-Speed Mode Timing Parameters
High-Speed Mode ID Parameter Min IC1 SCLH cycle time IC2 Setup time (repeated) START condition IC3 Hold time (repeated) START condition IC4 LOW Period of the SCLH Clock IC5 HIGH Period of SCLH Clock IC6 Data set-up time IC7 Data hold time IC8 Rise time of SCLH IC9 Rise time of SCLH signal after a repeated START condition and after an acknowledge bit IC10 Fall time of SCLH signal IC11 Rise time of SDAH signal IC12 Fall time of SDAH signal IC13 Set-up time for STOP condition IC14 Capacitive load for each bus line (Cb)
1
Unit Max 3.4 -- -- -- -- -- 70 40 80 40 80 80 -- 100 MHz ns ns ns ns ns ns ns ns ns ns ns ns pF
10 160 160 160 60 10 01 10 10 10 10 10 160 --
A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the falling edge of SCLH.
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3.7.7
I2C Module Timing Parameters
This section describes the timing parameters of the I2C Module. Figure 46 depicts the timing of I2C module, and Table 64 lists the I2C Module timing characteristics.
IC10 IC11 IC9
I2DAT IC2 IC8
I2CLK
IC4
IC7
IC3
START
IC10 IC6 IC1 IC5
IC11
START
STOP
START
Figure 46. I2C Bus Timing Table 64. I2C Module Timing Parameters
Fast Mode Standard Mode Supply Voltage = Supply Voltage = 2.7 V-3.3 V Unit 1.65 V-1.95 V, 2.7 V-3.3 V Min IC1 IC2 IC3 IC4 IC5 IC6 IC7 IC8 IC9 IC10 IC11 IC12
1
ID
Parameter
Max -- -- -- 3.452 -- -- -- -- -- 1000 300 400
Min 2.5 0.6 0.6 01 0.6 1.3 0.6 1003 1.3 20 + 0.1Cb4
Max -- -- -- 0.92 -- -- -- -- -- 300 300 400
I2CLK cycle time Hold time (repeated) START condition Set-up time for STOP condition Data hold time HIGH Period of I2CLK Clock LOW Period of the I2CLK Clock Set-up time for a repeated START condition Data set-up time Bus free time between a STOP and START condition Rise time of both I2DAT and I2CLK signals Fall time of both I2DAT and I2CLK signals Capacitive load for each bus line (Cb)
10 4.0 4.0 01 4.0 4.7 4.7 250 4.7 -- -- --
s s s s s s s
ns
s
ns ns pF
20 + 0.1Cb4 --
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal. If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released. 4 Cb = total capacitance of one bus line in pF.
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3.7.8
Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities: * Connectivity to relevant devices--cameras, displays, graphics accelerators, and TV encoders. * Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions. * Synchronization and control capabilities such as avoidance of tearing artifacts.
3.7.8.1
Sensor Interface Timings
There are three camera timing modes supported by the IPU. 3.7.8.1.1 BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards. This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus. 3.7.8.1.2 Gated Clock Mode
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See Figure 47.
Start of Frame nth frame Active Line n+1th frame
SENSB_VSYNC
SENSB_HSYNC SENSB_PIX_CLK SENSB_DATA[19:0] invalid invalid
1st byte
1st byte
Figure 47. Gated Clock Mode Timing Diagram
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A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the SENSB_VSYNC timing repeats. 3.7.8.1.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 3.7.8.1.2, "Gated Clock Mode"), except for the SENSB_HSYNC signal, which is not used. See Figure 48. All incoming pixel clocks are valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus.
Start of Frame nth frame n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK SENSB_DATA[19:0] invalid invalid
1st byte
1st byte
Figure 48. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 48 is that of a typical sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
3.7.8.2
Electrical Characteristics
Figure 49 depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by the IPU.
SENSB_PIX_CLK (Sensor Output) IP3 SENSB_DATA, SENSB_VSYNC, SENSB_HSYNC IP2
1/IP1
Figure 49. Sensor Interface Timing Diagram
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Table 65. Sensor Interface Timing Characteristics
ID IP1 IP2 IP3 Parameter Sensor output (pixel) clock frequency Data and control setup time Data and control holdup time Symbol Fpck Tsu Thd Min 0.01 3 2 Max 120 -- -- Unit MHz ns ns
3.7.8.3
IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 66 defines the mapping of the Display Interface Pins used during various supported video interface formats.
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Table 66. Video Signal Cross-Reference
i.MX51A LCD Comment1
Port Name (x=1,2)
RGB/TV Signal Allocation (Example) RGB, Signal Name 16-bit 18-bit 24 Bit 8-bit 16-bit 20-bit (General) RGB RGB RGB YCrCb2 YCrCb YCrCb DAT[0] DAT[1] DAT[2] DAT[3] DAT[4] DAT[5] DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] DAT[16] DAT[17] DAT[18] DAT[19] DAT[20] DAT[21] B[0] B[1] B[2] B[3] B[4] G[0] G[1] G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] -- -- -- -- -- -- B[0] B[1] B[2] B[3] B[4] B[5] G[0] G[1] G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] R[5] -- -- -- -- B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] Y/C[0] Y/C[1] Y/C[2] Y/C[3] Y/C[4] Y/C[5] Y/C[6] Y/C[7] -- -- -- -- -- -- -- -- -- -- -- -- -- -- C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] -- -- -- -- -- -- C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] Y[9] -- --
Smart Signal Name DAT[0] DAT[1] DAT[2] DAT[3] DAT[4] DAT[5] DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] -- -- -- -- -- --
DISPx_DAT0 DISPx_DAT1 DISPx_DAT2 DISPx_DAT3 DISPx_DAT4 DISPx_DAT5 DISPx_DAT6 DISPx_DAT7 DISPx_DAT8 DISPx_DAT9 DISPx_DAT10 DISPx_DAT11 DISPx_DAT12 DISPx_DAT13 DISPx_DAT14 DISPx_DAT15 DISPx_DAT16 DISPx_DAT17 DISPx_DAT18 DISPx_DAT19 DISPx_DAT20 DISPx_DAT21
The restrictions are as follows: a) There are maximal three continuous groups of bits that could be independently mapped to the external bus. Groups should not be overlapped. b) The bit order is expressed in each of the bit groups, for example B[0] = least significant blue pixel bit
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Table 66. Video Signal Cross-Reference (continued)
i.MX51A LCD Comment1
Port Name (x=1,2)
RGB/TV Signal Allocation (Example) RGB, Signal 16-bit 18-bit 24 Bit 8-bit Name 16-bit 20-bit (General) RGB RGB RGB YCrCb2 YCrCb YCrCb DAT[22] DAT[23] -- -- -- -- R[6] R[7] PixCLK -- -- -- -- -- -- --
Smart Signal Name -- -- -- -- -- --
DISPx_DAT22 DISPx_DAT23 DIx_DISP_CLK DIx_PIN1
VSYNC_IN May be required for anti-tearing
DIx_PIN2 DIx_PIN3 DIx_PIN4 DIx_PIN5 DIx_PIN6 DIx_PIN7 DIx_PIN8 DIx_D0_CS DIx_D1_CS DIx_PIN11 DIx_PIN12 DIx_PIN13 DIx_PIN14 DIx_PIN15 DIx_PIN16 DIx_PIN17
1 2
HSYNC VSYNC -- -- -- -- -- -- -- -- -- -- -- DRDY/DV -- Q
-- -- -- -- -- -- -- CS0 CS1 WR RD RS1 RS2 DRDY -- --
-- VSYNC out Additional frame/row synchronous signals with programmable timing
-- Alternate mode of PWM output for contrast or brightness control -- -- Register select signal Optional RS2 Data validation/blank, data enable Additional data synchronous signals with programmable features/timing
Signal mapping (both data and control/synchronization) is flexible. The table provides examples. This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported.
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Electrical Characteristics
3.7.8.4
IPU Display Interface Timing
The IPU Display Interface supports two kinds of display's accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly. 3.7.8.4.1 Synchronous Controls
The synchronous control is a signal that changes its value as a function either of a system or of an external clock. This control has a permanent period and a permanent wave form. There are special physical outputs to provide synchronous controls: * The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display. * The ipp_pin_1- ipp_pin_7 are general purpose synchronous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (like HSYNC/VSYCN etc.) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control's changing points with half DI_CLK resolution. A full description of the counters system is in the IPU chapter of the i.MX51 reference manual. 3.7.8.4.2 Asynchronous Controls
The asynchronous control is a data oriented signal that changes its a value with an output data according to an additional internal flags coming with the data. There are special physical outputs to provide asynchronous controls, as follows: * The ipp_d0_cs and ipp_d1_cspins are dedicated to provide chip select signals to two displays * The ipp_pin_11- ipp_pin_17 are general purpose asynchronous pins, that can be used to provide WR. RD, RS or any else data oriented signal to display. NOTE The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution.
3.7.8.5
3.7.8.5.1
Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface: * IPP_DISP_CLK--Clock to display * HSYNC--Horizontal synchronization
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* *
VSYNC--Vertical synchronization DRDY--Active data
All synchronous display controls are generated on base of an internal generated "local start point". The synchronous display controls can be placed on time axis with DI's offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point. 3.7.8.5.2 LCD Interface Functional Description
Figure 50 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is: * DI_CLK internal DI clock, used for calculation of other controls. * IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously. * HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC) * VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. (Usually IPP_PIN_3 is used as VSYNC) * DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. (For DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
VSYNC HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
HSYNC DRDY 1 IPP_DISP_CLK IPP_DATA 2 3 m-1 m
Figure 50. Interface Timing Diagram for TFT (Active Matrix) Panels
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Electrical Characteristics
3.7.8.5.3
TFT Panel Sync Pulse Timing Diagrams
Figure 51 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All shown on the figure parameters are programmable. All controls are started by corresponding internal events--local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC and DRDY signals.
IP13o IP5o IP8o IP8 IP7 IP5
DI clock IPP_DISP_CLK VSYNC HSYNC DRDY IPP_DATA IP9 local start point local start point local start point IP9o IP6 D0 D1 Dn IP10
Figure 51. TFT Panels Timing Diagram--Horizontal Sync Pulse
Figure 52 depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable.
Start of frame End of frame
IP13
VSYNC
HSYNC DRDY IP11
IP14 IP12
IP15
Figure 52. TFT Panels Timing Diagram--Vertical Sync Pulse
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Table 67 shows timing characteristics of signals presented in Figure 51 and Figure 52.
Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level)
ID IP5 IP6 Parameter Display interface clock period Display pixel clock period Symbol Tdicp Tdpcp Value (1) Description Display interface clock. IPP_DISP_CLK Unit ns ns
DISP_CLK_PER_PIXEL Time of translation of one pixel to display, x Tdicp DISP_CLK_PER_PIXEL--number of pixel components in one pixel (1.n). The DISP_CLK_PER_PIXEL is virtual parameter to define Display pixel clock period. The DISP_CLK_PER_PIXEL is received by DC/DI one access division to n components. (SCREEN_WIDTH) x Tdicp SCREEN_WIDTH--screen width in, interface clocks. horizontal blanking included. The SCREEN_WIDTH should be built by suitable DI's counter2. HSYNC_WIDTH--Hsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI's counter. BGXP--Width of a horizontal blanking before a first active data in a line. (in interface clocks). The BGXP should be built by suitable DI's counter. Width a horizontal blanking after a last active data in a line. (in interface clocks) FW--with of active line in interface clocks. The FW should be built by suitable DI's counter. SCREEN_HEIGHT-- screen height in lines with blanking The SCREEN_HEIGHT is a distance between 2 VSYNCs. The SCREEN_HEIGHT should be built by suitable DI's counter. VSYNC_WIDTH--Vsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI's counter BGYP--width of first Vertical blanking interval in line.The BGYP should be built by suitable DI's counter. width of second Vertical blanking interval in line.The FH should be built by suitable DI's counter.
IP7
Screen width time
Tsw
ns
IP8
HSYNC width time
Thsw
(HSYNC_WIDTH)
ns
IP9
Horizontal blank interval 1
Thbi1
BGXP x Tdicp
ns
IP10
Horizontal blank interval 2
Thbi2
(SCREEN_WIDTH BGXP - FW) x Tdicp
ns
IP12
Screen height
Tsh
(SCREEN_HEIGHT) x Tsw
ns
IP13
VSYNC width
Tvsw
VSYNC_WIDTH
ns
IP14
Vertical blank interval 1
Tvbi1
BGYP x Tsw
ns
IP15
Vertical blank interval 2
Tvbi2
(SCREEN_HEIGHT BGYP - FH) x Tsw
ns
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Table 67. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
ID IP5o Parameter Offset of IPP_DISP_CLK Symbol Todicp Value DISP_CLK_OFFSET x Tdiclk Description DISP_CLK_OFFSET-- offset of IPP_DISP_CLK edges from local start point, in DI_CLKx2 (0.5 DI_CLK Resolution) Defined by DISP_CLK counter VSYNC_OFFSET--offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLKx2 (0.5 DI_CLK Resolution).The VSYNC_OFFSET should be built by suitable DI's counter. HSYNC_OFFSET--offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLKx2 (0.5 DI_CLK Resolution).The HSYNC_OFFSET should be built by suitable DI's counter. DRDY_OFFSET-- offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLKx2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI's counter. Unit ns
IP13o Offset of VSYNC
Tovs
VSYNC_OFFSET x Tdiclk
ns
IP8o
Offset of HSYNC
Tohs
HSYNC_OFFSET x Tdiclk
ns
IP9o
Offset of DRDY
Todrdy
DRDY_OFFSET x Tdiclk
ns
1
Display interface clock period immediate value. DISP_CLK_PERIOD T diclk x ------------------------------------------------------ , DI_CLK_PERIOD Tdicp = T floor DISP_CLK_PERIOD + 0.5 0.5 , ----------------------------------------------------- diclk DI_CLK_PERIOD DISP_CLK_PERIOD for integer -----------------------------------------------------DI_CLK_PERIOD DISP_CLK_PERIOD for fractional -----------------------------------------------------DI_CLK_PERIOD
DISP_CLK_PERIOD--number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK DI_CLK_PERIOD--relation of between programing clock frequency and current system clock frequency Display interface clock period average value. DISP_CLK_PERIOD Tdicp = T diclk x -----------------------------------------------------DI_CLK_PERIOD
2
DI's counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI's registers directly (by name), but can be generated by corresponding DI's counter. The SCREEN_WIDTH is an input value for DI's HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH.
The maximal accuracy of UP/DOWN edge of controls is
Accuracy = ( 0.5 x T diclk ) 0.75ns
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Electrical Characteristics
The maximal accuracy of UP/DOWN edge of IPP_DATA is
Accuracy = T diclk 0.75ns
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed via registers. Figure 53 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are set via the Register.
IP20o IP20 VSYNC HSYNC DRDY other controls IPP_DISP_CLK
Tdicu IPP_DATA
Tdicd
IP16
IP17
IP19
IP18
local start point
Figure 53. Synchronous Display Interface Timing Diagram--Access Level Table 68. Synchronous Display Interface Timing Characteristics (Access Level)
ID IP16 IP17 IP18 IP19 IP20o Parameter Display interface clock low time Display interface clock high time Data setup time Data holdup time Control signals offset times (defines for each pin) Symbol Tckl Tckh Tdsu Tdhd Tocsu Min Tdicd-Tdicu-1.5 Tdicp-Tdicd+Tdicu-1.5 Tdicd-1.5 Tdicp-Tdicd-1.5 Tocsu-1.5 Typ1 Tdicd2-Tdicu3 Tdicp-Tdicd+Tdicu Tdicu Tdicp-Tdicu Tocsu Tocsu+1.5 Max Tdicd-Tdicu+1.5 Tdicp-Tdicd+Tdicu+1.5 -- -- Unit ns ns ns ns --
IP20
Tcsu Control signals setup time to display interface clock (defines for each pin)
Tdicd-1.5-Tocsu%Tdicp Tdicu
--
ns
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific.
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Electrical Characteristics
2
Display interface clock down time 2 x DISP_CLK_DOWN 1 Tdicd = -- T diclk x ceil ------------------------------------------------------------ DI_CLK_PERIOD 2
3
Display interface clock up time 2 x DISP_CLK_UP 1 Tdicu = -- T diclk x ceil -------------------------------------------------- DI_CLK_PERIOD 2
where CEIL(X) rounds the elements of X to the nearest integers towards infinity.
3.7.8.6
Interface to a TV Encoder
The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of the interface is described in Figure 54. * * * * * NOTE The frequency of the clock DISP_CLK is 27 MHz (within 10%) The HSYNC, VSYNC signals are active low. The DRDY signal is shown as active high. The transition to the next row is marked by the negative edge of the HSYNC signal. It remains low for a single clock cycle The transition to the next field/frame is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles -- At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide. At a transition is to an even field (of the same frame), they do not coincide.
--
*
The active intervals--during which data is transferred--are marked by the HSYNC signal being high.
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Electrical Characteristics DISP_CLK HSYNC VSYNC DRDY IPP_DATA Cb Y Cr Y Cb Y Cr
Pixel Data Timing HSYNC DRDY VSYNC Even Field HSYNC DRDY VSYNC 261 262 263 264 265 266 267 Odd Field 268 269 273 523 524 525 1 2 3 4 5 6 10
Odd Field Line and Field Timing - NTSC HSYNC DRDY VSYNC Even Field 621 622 623 624 625 1 2 3
Even Field
4
23
Odd Field
HSYNC DRDY VSYNC
308
309
310
311
312
313
314
315
316
336
Odd Field Line and Field Timing - PAL
Even Field
Figure 54. TV Encoder Interface Timing Diagram
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3.7.8.6.1
TV Encoder Performance Specifications
The TV encoder output specifications are shown in Table 69.
Table 69. TV Encoder Video Performance Specifications
Parameter DAC STATIC PERFORMANCE Resolution1 Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 10 1 0.6 2 Rload = 37.5 Ohm Rset = 1.05 kOhm 1.24 1.306 1.37 2 1 Bits LSBs LSBs % V Conditions Min Typ Max Unit
Channel-to-channel gain matching2 Full scale output voltage2
DAC DYNAMIC PERFORMANCE Spurious Free Dynamic Range (SFDR) Spurious Free Dynamic Range (SFDR) Fout = 3.38 MHz Fsamp = 216 MHz Fout = 9.28 MHz Fsamp = 297 MHz 59 54 dBc dBc
VIDEO PERFORMANCE IN SD MODE2, 3 Short Term Jitter (Line to Line) Long Term Jitter (Field to Field) Frequency Response 0-4.0 MHz 5.75 MHz Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) Hue Accuracy Color Saturation Accuracy Chroma AM Noise Chroma PM Noise Chroma Nonlinear Phase Chroma Nonlinear Gain Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality Flat field full bandwidth -0.1 -0.7 0.5 0.35 0.6 75 0.8 1.5 -70 -47 0.5 2.5 0.1 1.0 1.0 2.5 3.5 0.1 0 ns ns dB dB % % Degrees dB Degrees % dB dB Degrees % % % ns
VIDEO PERFORMANCE IN HD MODE2
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Table 69. TV Encoder Video Performance Specifications (continued)
Luma Frequency Response Chroma Frequency Response Luma Nonlinearity Chroma Nonlinearity Luma Signal-to-Noise Ratio Chroma Signal-to-Noise Ratio
1 2
0-30 MHz 0-15 MHz, YCbCr 422 mode
-0.7 TBD 2.6 2.2
0.1 TBD
dB dB % % dB dB
0-30 MHz 0-15 MHz
TBD TBD
Guaranteed by design Guaranteed by characterization 3 Rset = 1.05 kOhm
3.7.8.7
3.7.8.7.1
Asynchronous Interfaces
Standard Parallel Interfaces
The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU's internal control levels (0 or 1) by UP and DOWN are defined in Registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component) The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines. The access to a display is realized by the following: * CS (IPP_CS) chip select * WR (IPP_PIN_11) write strobe * RD (IPP_PIN_12) read strobe * RS (IPP_PIN_13) Register select (A0) Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 55, Figure 56, Figure 57, and Figure 58. The timing images correspond to active-low IPP_CS, WR and RD signals. Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing of suitable access sizes. There are no minimal/maximal hold/setup time hard defined by DI. Each control signal can be switched at any time during access size.
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Electrical Characteristics IPP_CS
RS WR RD IPP_DATA
Burst access mode with sampling by CS signal IPP_CS
RS WR RD IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 55. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram
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IPP_CS
RS WR RD
IPP_DATA Burst access mode with sampling by WR/RD signals IPP_CS
RS WR RD IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 56. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram
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IPP_CS
RS WR (READ/WRITE) RD (ENABLE) IPP_DATA
Burst access mode with sampling by CS signal IPP_CS
RS WR (READ/WRITE) RD (ENABLE) IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 57. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram
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IPP_CS
RS WR (READ/WRITE) RD (ENABLE) IPP_DATA
Burst access mode with sampling by ENABLE signal IPP_CS
RS WR (READ/WRITE) RD (ENABLE) IPP_DATA
Single access mode (all control signals are not active for one display interface clock after each display access)
Figure 58. Asynchronous Parallel System 68k Interface (Type 2) TIming Diagram
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Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 59 shows timing of the parallel interface with IPP_WAIT control.
DI clock IPP_CS
IPP_DATA WR RD IPP_WAIT IPP_DATA_IN IP39 waiting waiting
Figure 59. Parallel Interface Timing Diagram--Read Wait States
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3.7.8.7.2
Asynchronous Parallel Interface Timing Parameters
Figure 60 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces. Table 71 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register).
IP29 IP35 IP33 IP36 IP34 IP47 IP30 IP31 IP32
DI clock IPP_CS
RS WR RD IPP_DATA A0 D0 D1 D2 IP28a local start point local start point local start point IP28d local start point IP27 local start point IP37 D3 IP38
PP_DATA_IN
Figure 60. Asynchronous Parallel Interface Timing Diagram Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID IP27 IP28a IP28d IP29 IP30 IP31 Parameter Read system cycle time Symbol Tcycr Value ACCESS_SIZE_# ACCESS_SIZE_# ACCESS_SIZE_# UP# UP# DOWN# Description predefined value in DI REGISTER predefined value in DI REGISTER predefined value in DI REGISTER RS strobe switch, predefined value in DI REGISTER CS strobe switch, predefined value in DI REGISTER CS strobe release, predefined value in DI REGISTER Unit ns ns ns ns ns --
Address Write system cycle time Tcycwa Data Write system cycle time RS start CS start CS hold Tcycwd Tdcsrr Tdcsc Tdchc
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Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level) (continued)
ID IP32 IP33 IP34 IP35 IP36 IP37 RS hold Read start Read hold Write start Controls hold time for write Slave device data delay1 Parameter Symbol Tdchrr Tdcsr Tdchr Tdcsw Tdchw Tracc Value DOWN# UP# DOWN# UP# DOWN# Delay of incoming data Description RS strobe release, predefined value in DI REGISTER read strobe switch, predefined value in DI REGISTER read strobe release signal, predefined value in DI REGISTER write strobe switch, predefined value in DI REGISTER write strobe release, predefined value in DI REGISTER Physical delay of display's data, defined from Read access local start point Unit -- ns ns ns ns ns
IP38 IP47
1This
Slave device data hold time3 Read time point13
Troh Tdrp
Hold time of data on the buss Time that display read data is valid in input bus Data sampling point Point of input data sampling by DI, predefined in DC Microcode
ns --
parameter is a requirement to the display connected to the IPU.
Table 71. Asynchronous Parallel Interface Timing Parameters (Access Level)
ID Parameter Symbol Tcycr Tcycw Tdcsrr Tdcsc Tdchc Tdchrr Tdcsr Tdchr Min Tdicpr-1.5 Tdicpw-1.5 Tdicurs-1.5 Tdicucs-1.5 TdicdcsTdicucs-1.5 Tdicdrs-Tdicurs-1.5 Tdicur-1.5 Tdicdr-Tdicur-1.5 Tdicuw-1.5 Tdicdw-Tdicuw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicpr2 Tdicpw 3 Tdicurs Tdicur Tdicdcs4-Tdicucs5 Tdicdrs6-Tdicurs7 Tdicur Tdicdr8-Tdicur9 Tdicuw Tdicpw 10-Tdicuw11 -- -- Typ1 Tdicpr+1.5 Tdicpw+1.5 Tdicurs+1.5 Tdicucs+1.5 Tdicdcs-Tdicucs+1.5 Tdicdrs-Tdicurs+1.5 Tdicur+1.5 Tdicdr-Tdicur+1.5 Tdicuw+1.5 Tdicdw-Tdicuw+1.5 Tdrp13-Tlbd14-Tdicur-1.5 Tdicpr-Tdicdr-1.5 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
IP27 Read system cycle time IP28 Write system cycle time IP29 RS start IP30 CS start IP31 CS hold IP32 RS hold IP33 Controls setup time for read IP34 Controls hold time for read
IP35 Controls setup time for write Tdcsw IP36 Controls hold time for write IP37 Slave device data delay12 IP38 Slave device data hold time8 Tdchw Tracc Troh
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Table 71. Asynchronous Parallel Interface Timing Parameters (Access Level) (continued)
ID Parameter Symbol Tswait Tdrp Tdrp-1.5 Min -- Tdrp Typ1 -- Tdrp+1.5 Max -- Unit -- ns
IP39 Setup time for wait signal IP47 Read time point13
1The
exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2 Display period value for read Tdicpr = T DI_CLK DI_ACCESS_SIZE_# x ceil -------------------------------------------------------DI_CLK_PERIOD
ACCESS_SIZE is predefined in REGISTER 3 Display period value for write DI_ACCESS_SIZE_# Tdicpw = T DI_CLK x ceil -------------------------------------------------------DI_CLK_PERIOD ACCESS_SIZE is predefined in REGISTER 4Display control down for CS 2 x DISP_DOWN_# 1 Tdicdcs = -- T x ceil ---------------------------------------------------- DI_CLK_PERIOD 2 DI_CLK DISP_DOWN is predefined in REGISTER 5Display control up for CS 2 x DISP_UP_# 1 Tdicucs = -- T DI_CLK x ceil ---------------------------------------------- DI_CLK_PERIOD 2 DISP_UP is predefined in REGISTER 6Display control down for RS 2 x DISP_DOWN_# 1 Tdicdrs = -- T DI_CLK x ceil ---------------------------------------------------- DI_CLK_PERIOD 2 DISP_DOWN is predefined in REGISTER 7Display control up for RS 2 x DISP_UP_# 1 Tdicurs = -- T x ceil ---------------------------------------------- DI_CLK_PERIOD 2 DI_CLK DISP_UP is predefined in REGISTER 8Display control down for read 2 x DISP_DOWN_# 1 Tdicdr = -- T DI_CLK x ceil ---------------------------------------------------- DI_CLK_PERIOD 2 DISP_DOWN is predefined in REGISTER
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Electrical Characteristics
9
Display control up for read 2 x DISP_UP_# 1 Tdicur = -- T DI_CLK x ceil ---------------------------------------------- DI_CLK_PERIOD 2
DISP_UP is predefined in REGISTER 10 Display control down for read 2 x DISP_DOWN_# 1 Tdicdrw = -- T x ceil ---------------------------------------------------- DI_CLK_PERIOD 2 DI_CLK DISP_DOWN is predefined in REGISTER 11 Display control up for write 2 x DISP_UP_# 1 Tdicuw = -- T DI_CLK x ceil ---------------------------------------------- DI_CLK_PERIOD 2 DISP_UP is predefined in REGISTER 12This parameter is a requirement to the display connected to the IPU 13Data read point Tdrp = T DISP#_READ_EN x ceil ------------------------------------------------
DI_CLK_PERIOD Note: DISP#_READ_EN--operand of DC's MICROCDE READ command to sample incoming data 14Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific.
DI_CLK
3.7.8.8
Standard Serial Interfaces
The IPU supports the following types of asynchronous serial interfaces: 1. 3-wire (with bidirectional data line). 2. 4-wire (with separate data input and output lines). 3. 5-wire type 1 (with sampling RS by the serial clock). 4. 5-wire type 2 (with sampling RS by the chip select signal). The IPU has four independent outputs and one input. The port can be configured to provide 3, 4, or 5-wire interfaces. Figure 61 depicts the timing diagram of the 3-wire serial interface. The timing diagrams correspond to active-low IPP#_CS signal and the straight polarity of the IPP_CLK signal. For this interface, a bidirectional data line is used outside the chip. The IPU still uses separate input and output data lines (IPP_IND_DISPB_SD_D and IPP_DO_DISPB_SD_D). The I/O mux should provide joining the internal data lines to the bidirectional external line according to the IPP_OBE_DISPB_SD_D signal provided by the IPU.
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Electrical Characteristics
DISPB_D#_CS
programed delay
programed delay
DISPB_SD_D_CLK DISPB_SD_D RW RS D7 D6 D5 D4 D3 D2 D1 D0
Preamble
Input or output data
Figure 61. 3-Wire Serial Interface Timing Diagram
Figure 62 depicts timing diagram of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the chip.
Write DISPB_D#_CS programed delay programed delay
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) RW RS D7 D6 D5 D4 D3 D2 D1 D0
Output data
Read DISPB_D#_CS programed delay programed delay
DISPB_SD_D_CLK DISPB_SD_D (Output) RW RS
Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0
Input data
Figure 62. 4-Wire Serial Interface Timing Diagram
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Figure 63 depicts timing of the 5-wire serial interface. For this interface, a separate RS line is added.
Write DISPB_D#_CS programed delay programed delay
DISPB_SD_D_CLK DISPB_SD_D (Output) RW D7 D6 D5 D4 D3 D2 D1 D0
Preamble DISPB_SD_D (Input) programed delay
Output data
DISPB_SER_RS
Read DISPB_D#_CS programed delay programed delay
DISPB_SD_D_CLK DISPB_SD_D (Output) Preamble DISPB_SD_D (Input) D7 D6 D5 D4 D3 D2 D1 D0 RW
DISPB_SER_RS
programed delay
Input data
Figure 63. 5-Wire Serial Interface Timing Diagram
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3.7.8.8.1
Asynchronous Serial Interface Timing Parameters
Figure 64 depicts timing of the serial interface. Table 72 shows timing characteristics at display access level.
IP73 IP72 DI clock IPP_DISPB_DO_SD_D IPP_DO_DISPB_SER_CS IP71 IP70
IPP_DO_DISPB_SER_RS
IP68 IP58
IPP_IND_DISPB_SD_D IP59 IP60, IP64, IP66 IP69 IP50, IP52 IP55, IP57, IP61 IP54, IP56, IP65, IP67
IPP_DO_DISPB_SD_D_CLK local start point IP51,53 IP48, IP49, IP62, IP63
Figure 64. Asynchronous Serial Interface Timing Diagram Table 72. Asynchronous Serial Interface Timing Characteristics (Access Level)
ID Parameter Symbol Tcycr Tcycw Trl Trh Tdicpr-1.5 Tdicpw-1.5 Tdicdr-Tdicur-1.5 Min Typ1 Tdicpr2 Tdicpw3 Tdicdr4-Tdicur5 Max Tdicpr+1.5 Tdicpw+1.5 Tdicdr-Tdicur+1.5 Tdicpr-Tdicdr+Tdicur+ 1.5 Unit ns ns ns ns
IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width
Tdicpr-Tdicdr+Tdicur-1.5 Tdicpr-Tdicdr+ Tdicur
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Table 72. Asynchronous Serial Interface Timing Characteristics (Access Level) (continued)
ID Parameter Symbol Twl Twh Tdcsr Tdchr Min Tdicdw-Tdicuw-1.5 Tdicpw-Tdicdw+ Tdicuw-1.5 Tdicur-1.5 Tdicpr-Tdicdr-1.5 Tdicuw-1.5 Tdicpw-Tdicdw-1.5 0 Tdrp-Tlbd-Tdicdr+1.5 Tdicdw-1.5 Tdicpw-Tdicdw-1.5 Tdicpr-1.5 Tdicpw-1.5 Tdicdr-1.5 Tdicur-1.5 Tdicdw-1.5 Tdicuw-1.5 Tdrp-1.5 Toclk-1.5 Tdicurs-1.5 Tdicdrs -1.5 Tdicdw Tdicpw-Tdicdw Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Toclk Tdicurs Tdicdrs Tdicucs Tdicdcs Tdicpr+1.5 Tdicpw+1.5 Tdicdr+1.5 Tdicur+1.5 Tdicdw+1.5 Tdicuw+1.5 Tdrp+1.5 Toclk+1.5 Tdicurs+1.5 Tdicdrs+1.5 Tdicucs+1.5 Tdicdcs+1.5 Typ1 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
IP52 Write clock low pulse width IP53 Write clock high pulse width IP54 Controls setup time for read IP55 Controls hold time for read
Tdicdw6-Tdicuw7 Tdicdw-Tdicuw+1.5 Tdicpw-Tdicdw+ Tdicpw-Tdicdw+ Tdicuw Tdicuw+1.5 Tdicur Tdicpr-Tdicdr Tdicuw Tdicpw-Tdicdw -- --
9
-- -- -- -- Tdrp -Tlbd -Tdicur-1.5 Tdicpr-Tdicdr-1.5 -- --
10
IP56 Controls setup time for write Tdcsw IP57 Controls hold time for write IP58 Slave device data delay8 Tdchw Tracc
IP59 Slave device data hold time8 Troh IP60 Write data setup time IP61 Write data hold time IP62 Read period2 Tds Tdh Tdicpr Tdicpw Tdicdr Tdicur Tdicdw Tdicuw Tdrp Toclk Tdicurs Tdicdrs
IP63 Write period3 IP64 Read down time4
IP65 Read up time5 IP66 Write down time6
IP67 Write up time7 IP68 Read time point9
IP69 Clock offset11 IP70 RS up time12
IP71 RS down time13 IP72 CS up time14
Tdicucs Tdicucs -1.5 Tdicdcs Tdicdcs -1.5
IP73 CS down time15
1
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. 2Display interface clock period value for read DISP#_IF_CLK_PER_RD Tdicpr = TDI_CLK x ceil -------------------------------------------------------------------DI_CLK_PERIOD
3Display
interface clock period value for write DISP#_IF_CLK_PER_WR Tdicpw = T DI_CLK x ceil --------------------------------------------------------------------DI_CLK_PERIOD
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4
Display interface clock down time for read 2 x DISP_DOWN_# 1 Tdicdr = -- T DI_CLK x ceil ---------------------------------------------------- DI_CLK_PERIOD 2
5
Display interface clock up time for read 2 x DISP_UP_# 1 Tdicur = -- T DI_CLK x ceil ---------------------------------------------- DI_CLK_PERIOD 2
6
Display interface clock down time for write 2 x DISP_DOWN_# 1 Tdicdw = -- T DI_CLK x ceil ---------------------------------------------------- DI_CLK_PERIOD 2
7
Display interface clock up time for write 2 x DISP_UP_# 1 Tdicuw = -- T DI_CLK x ceil ---------------------------------------------- DI_CLK_PERIOD 2
8This 9Data
parameter is a requirement to the display connected to the IPU read point DISP_READ_EN Tdrp = T DI_CLK x ceil ---------------------------------------------DI_CLK_PERIOD
DISP_RD_EN is predefined in REGISTER 10Loop back delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a chip-level output delay, board delays, a chip-level input delay, an IPU input delay. This value is chip specific. 11Display interface clock offset value Toclk = T DI_CLK DISP_CLK_OFFSET x ceil ------------------------------------------------------DI_CLK_PERIOD
12Display
CLK_OFFSET is predefined in REGISTER RS up time DISP_RS_UP_# Tdicurs = T DI_CLK x ceil ---------------------------------------------DI_CLK_PERIOD DISP_RS_UP is predefined in REGISTER RS down time DISP_RS_DOWN_# Tdicdrs = T DI_CLK x ceil ----------------------------------------------------DI_CLK_PERIOD DISP_RS_DOWN is predefined in REGISTER RS up time DISP_CS_UP_# Tdicucs = T DI_CLK x ceil ---------------------------------------------DI_CLK_PERIOD DISP_CS_UP is predefined in REGISTER
13Display
14Display
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15
Display RS down time DISP_CS_DOWN_# Tdicdcs = ( T DI_CLK x ceil) -----------------------------------------------------DI_CLK_PERIOD
DISP_CS_DOWN is predefined in REGISTER.
3.7.9
1-Wire Timing Parameters
Figure 65 depicts the RPP timing, and Table 73 lists the RPP timing parameters.
1-WIRE Tx "Reset Pulse" One-Wire bus (BATT_LINE) DS2502 Tx "Presence Pulse" OW2
OW1
OW3 OW4
Figure 65. Reset and Presence Pulses (RPP) Timing Diagram Table 73. RPP Sequence Delay Comparisons Timing Parameters
ID OW1 OW2 OW3 OW4 Parameters Reset Time Low Presence Detect High Presence Detect Low Reset Time High Symbol tRSTL tPDH tPDL tRSTH Min 480 15 60 480 Typ 511 -- -- 512 Max -- 60 240 -- Unit s s s s
Figure 66 depicts Write 0 Sequence timing, and Table 74 lists the timing parameters.
OW6 One-Wire bus (BATT_LINE)
OW5
Figure 66. Write 0 Sequence Timing Diagram Table 74. WR0 Sequence Timing Parameters
ID OW5 OW6 Parameter Write 0 Low Time Transmission Time Slot Symbol tWR0_low tSLOT Min 60 OW5 Typ 100 117 Max 120 120 Unit s s
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Figure 67 depicts Write 1 Sequence timing, Figure 68 depicts the Read Sequence timing, and Table 75 lists the timing parameters.
OW8 One-Wire bus (BATT_LINE)
OW7
Figure 67. Write 1 Sequence Timing Diagram
OW8 One-Wire bus (BATT_LINE)
OW7 OW9
Figure 68. Read Sequence Timing Diagram Table 75. WR1 /RD Timing Parameters
ID OW7 OW8 OW9 Parameter Write /Read Low Time Transmission Time Slot Release Time Symbol tLOW1 tSLOT tRELEASE Min 1 60 15 Typ 5 117 -- Max 15 120 45 Unit s s s
3.7.10
Pulse Width Modulator (PWM) Timing Parameters
This section describes the electrical information of the PWM.The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.
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Figure 69 depicts the timing of the PWM, and Table 76 lists the PWM timing parameters.
2a System Clock 2b 3a 4a PWM Output 1 3b
4b
Figure 69. PWM Timing Table 76. PWM Output Timing Parameter
Ref. No. 1 2a 2b 3a 3b 4a 4b
1
Parameter System CLK frequency1 Clock high time Clock low time Clock fall time Clock rise time Output delay time Output setup time
Min 0 12.29 9.91 -- -- -- 8.71
Max ipg_clk -- -- 0.5 0.5 9.37 --
Unit MHz ns ns ns ns ns ns
CL of PWMO = 30 pF
3.7.11
P-ATA Timing Parameters
This section describes the timing parameters of the Parallel ATA module which are compliant with ATA/ATAPI-6 specification. Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA module interface consist of a total of 29 pins, Some pins act on different function in different transfer mode. There are different requirements of timing relationships among the function pins conform with ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers. Table 77 and Figure 70 define the AC characteristics of all the P-ATA interface signals on all data transfer modes.
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ATA Interface Signals
SI2
SI1
Figure 70. P-ATA Interface Signals Timing Diagram Table 77. AC Characteristics of All Interface Signals
ID SI1 SI2 SI3
1
Parameter Rising edge slew rate for any signal on ATA interface.1 Falling edge slew rate for any signal on ATA interface (see note) Host interface signal capacitance at the host connector
Symbol Srise Sfall Chost
Min -- -- --
Max 1.25 1.25 20
Unit V/ns V/ns pF
SRISE and SFALL shall meet this requirement when measured at the sender's connector from 10-90% of full signal amplitude with all capacitive loads from 15-40 pF where all signals have the same capacitive load value.
The user needs to use level shifters for 5.0 V compatibility on the ATA interface. The i.MX51 P-ATA interface is 3.3 V compatible. The use of bus buffers introduces delay on the bus and introduces skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers. Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus. According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals. When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.
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In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX51 P-ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 78 shows ATA timing parameters.
Table 78. P-ATA Timing Parameters
Name T ti_ds Bus clock period (ipg_clk_ata) Set-up time ata_data to ata_iordy edge (UDMA-in only) UDMA0 UDMA1 UDMA2, UDMA3 UDMA4 UDMA5 ti_dh Hold time ata_iordy edge to ata_data (UDMA-in only) UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 UDMA5 Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en Set-up time ata_data to bus clock L-to-H Set-up time ata_iordy to bus clock H-to-L Hold time ata_iordy to bus clock H to L Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) Max buffer propagation delay Cable propagation delay for ata_data Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack Max difference in cable propagation delay between ata_iordy and ata_data (read) Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) Max difference in cable propagation delay without accounting for ground bounce 15 ns 10 ns 7 ns 5 ns 4 ns 5.0 ns 4.6 ns 12.0 ns Description Value/ Contributing Factor1 Peripheral clock frequency
tco
tsu tsui thi tskew1
8.5 ns 8.5 ns 2.5 ns 7 ns
tskew2
Transceiver
tskew3 tbuf tcable1 tcable2 tskew4 tskew5 tskew6
1
Transceiver Transceiver Cable Cable Cable Cable Cable
Values provided where applicable.
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3.7.11.1
PIO Mode Read Timing
Figure 71 shows timing for PIO read, and Table 79 lists the timing parameters for PIO read.
Figure 71. PIO Read Timing Diagram Table 79. PIO Read Timing Parameters
ATA Parameter Parameter from Figure 71 t1 t2 t9 t5 t6 tA trd t1 t2r t9 t5 t6 tA trd1 Value t1 (min) = time_1 x T - (tskew1 + tskew2 + tskew5) t2 min) = time_2r x T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 x T - (tskew1 + tskew2 + tskew6) t5 (min) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 0 tA (min) = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2xtbuf) trd1 (max) = (-trd) + (tskew3 + tskew4) trd1 (min) = (time_pio_rdx - 0.5)xT - (tsu + thi) (time_pio_rdx - 0.5) x T > tsu + thi + tskew3 + tskew4 t0 (min) = (time_1 + time_2 + time_9) x T Controlling Variable time_1 time_2r time_3 If not met, increase time_2 -- time_ax time_pio_rdx
t0
--
time_1, time_2r, time_9
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Figure 72 shows timing for PIO write, and Table 80 lists the timing parameters for PIO write.
Figure 72. Multi-word DMA (MDMA) Timing Table 80. PIO Write Timing Parameters
ATA Parameter Parameter from Figure 72 t1 t2 t9 t3 t4 tA t0 -- -- t1 t2w t9 -- t4 tA -- -- -- t1 (min) = time_1 Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 -- --
x T - (tskew1 + tskew2 + tskew5) t2 (min) = time_2w x T - (tskew1 + tskew2 + tskew5) t9 (min) = time_9 x T - (tskew1 + tskew2 + tskew6)
t3 (min) = (time_2w - time_on)x T - (tskew1 + tskew2 +tskew5)
x T - tskew1 tA = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2xtbuf) t0(min) = (time_1 + time_2 + time_9) x T
t4 (min) = time_4 Avoid bus contention when switching buffer on by making ton long enough Avoid bus contention when switching buffer off by making toff long enough
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Figure 73 shows timing for MDMA read, Figure 74 shows timing for MDMA write, and Table 81 lists the timing parameters for MDMA read and write.
Figure 73. MDMA Read Timing Diagram
Figure 74. MDMA Write Timing Diagram Table 81. MDMA Read and Write Timing Parameters
Parameter from Figure 73, Figure 74 tm td, td1 tk -- tgr tfr -- -- -- tm (min) = ti (min) = time_m
ATA Parameter
Value
Controlling Variable
tm, ti td tk t0 tg(read) tf(read) tg(write) tf(write) tL
x T - (tskew1 + tskew2 + tskew5) td1.(min) = td (min) = time_d x T - (tskew1 + tskew2 + tskew6) tk.(min) = time_k x T - (tskew1 + tskew2 + tskew6) t0 (min) = (time_d + time_k) x T
tgr (min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr.(min-drive) = td - te(drive) tfr (min-drive) = 0 tg (min-write) = time_d x T - (tskew1 + tskew2 + tskew5) tf (min-write) = time_k
time_m time_d time_k time_d, time_k time_d -- time_d time_k time_d, time_k
x T - (tskew1 + tskew2 + tskew6)
tL (max) = (time_d + time_k-2)xT - (tsu + tco + 2xtbuf + 2xtcable2)
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Table 81. MDMA Read and Write Timing Parameters (continued)
Parameter from Figure 73, Figure 74 tkjn ton toff
ATA Parameter
Value
Controlling Variable
tn, tj --
tn= tj= tkjn = (max(time_k,. time_jn) x T - (tskew1 + tskew2 + tskew6) ton = time_on x T - tskew1 toff = time_off x T - tskew1
time_jn --
3.7.11.2
Ultra DMA (UDMA) Input Timing
Figure 75 shows timing when the UDMA in transfer starts, Figure 76 shows timing when the UDMA in host terminates transfer, Figure 77 shows timing when the UDMA in device terminates transfer, and Table 82 lists the timing parameters for UDMA in burst.
Figure 75. UDMA In Transfer Starts Timing Diagram
Figure 76. UDMA In Host Terminates Transfer Timing Diagram
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Figure 77. UDMA In Device Terminates Transfer Timing Diagram Table 82. UDMA In Burst Timing Parameters
Parameter from Figure 75, Figure 76, Figure 77 tack tenv tds1 tdh1 tc1 trp tx11 tmli1 tzah tdzfs tcvh ton toff2
ATA Parameter
Description
Controlling Variable
tack tenv tds tdh tcyc trp -- tmli tzah tdzfs tcvh --
1
tack (min) = (time_ack x T) - (tskew1 + tskew2) tenv (min) = (time_env x T) - (tskew1 + tskew2) tenv (max) = (time_env x T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) - ti_dh > 0 (tcyc - tskew) > T
time_ack time_env tskew3, ti_ds, ti_dh should be low enough T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh --
x T - (tskew1 + tskew2 + tskew6) (time_rp x T) - (tco + tsu + 3T + 2 xtbuf + 2xtcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4) x T tzah (min) = (time_zah + 0.4) x T tdzfs = (time_dzfs x T) - (tskew1 + tskew2) tcvh = (time_cvh xT) - (tskew1 + tskew2) ton = time_on x T - tskew1 toff = time_off x T - tskew1
trp (min) = time_rp
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2 Make ton and toff big enough to avoid bus contention.
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3.7.11.3
UDMA Output Timing
Figure 78 shows timing when the UDMA out transfer starts, Figure 79 shows timing when the UDMA out host terminates transfer, Figure 80 shows timing when the UDMA out device terminates transfer, and Table 83 lists the timing parameters for UDMA out burst.
Figure 78. UDMA Out Transfer Starts Timing Diagram
Figure 79. UDMA Out Host Terminates Transfer Timing Diagram
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Figure 80. UDMA Out Device Terminates Transfer Timing Diagram Table 83. UDMA Out Burst Timing Parameters
Parameter from Figure 78, Figure 79, Figure 80 tack tenv tdvs tdvh tcyc -- trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff tack (min) = (time_ack
ATA Parameter
Value
Controlling Variable
tack tenv tdvs tdvh tcyc t2cyc trfs1 -- tss tmli tli tli tli tcvh --
x T) - (tskew1 + tskew2) tenv (min) = (time_env x T) - (tskew1 + tskew2) tenv (max) = (time_env x T) + (tskew1 + tskew2) tdvs = (time_dvs x T) - (tskew1 + tskew2) tdvs = (time_dvh x T) - (tskew1 + tskew2) tcyc = time_cyc x T - (tskew1 + tskew2) t2cyc = time_cyc x 2 x T trfs = 1.6 x T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs x T - (tskew1) tss = time_ss x T - (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli) x T - (tskew1 + tskew2)
tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh xT) - (tskew1 + tskew2) ton = time_on x T - tskew1 toff = time_off x T - tskew1
time_ack time_env time_dvs time_dvh time_cyc time_cyc -- time_dzfs time_ss -- -- -- -- time_cvh --
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3.7.12
SIM (Subscriber Identification Module) Timing
This section describes the electrical parameters of the SIM module. Each SIM module interface consists of 12 signals (two separate ports each containing six signals). Typically a a port uses five signals. The interface is designed to be used with synchronous SIM cards meaning the SIM module provides the clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rxdata rate, however the SIM module can work with CLK frequencies of 16 times the Tx/Rx data rate. There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard UART data exchanges. All six signals (5 for bi-directional Tx/Rx) of the SIM module are asynchronous to each other. There are no required timing relationships between signals in normal mode. The SIM card is initiated by the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO-7816 defines reset and power-down sequences. (For detailed information, see ISO-7816.) Table 84 defines the general timing requirements for the SIM interface.
Table 84. SIM Timing Parameters, High Drive Strength
ID SI1 SI2 SI3 SI4 SI5 SI6
1 2
Parameter SIM Clock Frequency (SIMx_CLKy)1, SIM Clock Rise Time (SIMx_CLKy)2
Symbol Sfreq Srise Sfall Strans Tr/Tf Tr/Tf
Min 0.01 -- -- 10 -- --
Max 25 0.09x(1/Sfreq) 0.09x(1/Sfreq) 25 1 1
Unit MHz ns ns ns
SIM Clock Fall Time (SIMx_CLKy)3 SIM Input Transition Time (SIMx_DATAy_RX_TX, SIMx_SIMPDy) SIM I/O Rise Time / Fall Time(SIMx_DATAy_RX_TX)4 SIM RST Rise Time / Fall Time(SIMx_RSTy)5
s s
50% duty cycle clock With C = 50 pF 3 With C = 50 pF 4 With Cin = 30 pF, Cout = 30 pF 5 With Cin = 30 pF
1/SI1
SIMx_CLKy
SI3
SI2
Figure 81. SIM Clock Timing Diagram
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3.7.12.1
3.7.12.1.1
Reset Sequence
Cards with internal reset
The sequence of reset for this kind of SIM Cards is as follows (see Figure 82): * After power up, the clock signal is enabled on SIMx_CLKy(time T0) * After 200 clock cycles, RX must be high. * The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0.
SIMx_SVENy
SIMx_CLKy
SIMx_DATAy_RX_TX 1 2 T0
response
1 400 clock cycles < 2
< 200 clock cycles < 40000 clock cycles
Figure 82. Internal-Reset Card Reset Sequence
3.7.12.1.2
Cards with Active Low Reset
The sequence of reset for this kind of card is as follows (see Figure 83): * After power-up, the clock signal is enabled on SIMx_CLKy (time T0) * After 200 clock cycles, SIMx_DATAy_RX_TX must be high. * SIMx_RSTy must remain Low for at least 40000 clock cycles after T0 (no response is to be received on RX during those 40000 clock cycles) * SIMx_RSTy is set High (time T1) * SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1.
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Electrical Characteristics
SIMx_SVENy
SIMx_RSTy
SIMx_CLKy
SIMx_DATAy_RX_TX 1 2
response
3 T0 T1
3
1 400 clock cycles < 400000 clock cycles < 2 3
< 200 clock cycles < 40000 clock cycles
Figure 83. Active-Low-Reset Cards Reset Sequence
3.7.12.2
Power Down Sequence
Power down sequence for SIM interface is as follows: * SIMx_SIMPDy port detects the removal of the SIM Card * SIMx_RSTy goes Low * SIMx_CLKy goes Low * SIMx_DATAy_RX_TX goes Low * SIMx_SVENy goes Low Each of these steps is done in one CKIL period (usually 32 kHz). Power-down can be started because of a SIM Card removal detection or launched by the processor. Find in the table and figure below the usual timing requirements for this sequence, with Fckil = CKIL frequency value.
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Electrical Characteristics
SI10 SIMx_SIMPDy
SIMx_RSTy
SI7 SIMx_CLKy SI8 SIMx_DATAy_RX_TX
SI9 SIMx_SVENy
Figure 84. SmartCard Interface Power Down AC Timing Table 85. Timing Requirements for Power Down Sequence
ID SI7 SI8 SI9 SI10 Parameter SIM reset to SIM clock stop SIM reset to SIM TX data low SIM reset to SIM voltage enable low SIM presence detect to SIM reset low Symbol Srst2clk Srst2dat Srst2ven Spd2rst Min 0.9x1/Fckil 1.8x1/Fckil 2.7x1/Fckil 0.9x1/Fckil Max 1.1x1/Fckil 2.2x1/Fckil 3.3x1/Fckil 1.1x1/Fckil Unit ns ns ns ns
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Electrical Characteristics
3.7.13
SCAN JTAG Controller (SJC) Timing Parameters
Figure 85 depicts the SJC test clock input timing. Figure 86 depicts the SJC boundary scan timing. Figure 87 depicts the SJC test access port. Signal parameters are listed in Table 86.
SJ1 SJ2 TCK (Input) SJ3 VIH VIL SJ3 VM SJ2 VM
Figure 85. Test Clock Input Timing Diagram
TCK (Input) VIL SJ4 Data Inputs SJ6 Data Outputs SJ7 Data Outputs SJ6 Data Outputs Output Data Valid Output Data Valid SJ5
VIH
Input Data Valid
Figure 86. Boundary Scan (JTAG) Timing Diagram
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Electrical Characteristics TCK (Input) VIL SJ8 TDI TMS (Input) SJ10 TDO (Output) SJ11 TDO (Output) SJ10 TDO (Output) Output Data Valid Output Data Valid Input Data Valid SJ9
VIH
Figure 87. Test Access Port Timing Diagram
TCK (Input) SJ13 TRST (Input)
SJ12
Figure 88. TRST Timing Diagram Table 86. JTAG Timing
All Frequencies ID Parameter1,2 Min SJ0 SJ1 SJ2 SJ3 SJ4 SJ5 SJ6 SJ7 SJ8 TCK frequency of operation 1/(3*TDC)1 TCK cycle time in crystal mode TCK clock pulse width measured at VM2 TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time 0.001 45 22.5 -- 5 24 -- -- 5 Max 22 -- -- 3 -- -- 40 40 -- MHz ns ns ns ns ns ns ns ns Unit
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Electrical Characteristics
Table 86. JTAG Timing (continued)
All Frequencies ID Parameter1,2 Min SJ9 SJ10 SJ11 SJ12 SJ13
1 2
Unit Max -- 44 44 -- -- ns ns ns ns ns
TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low
25 -- -- 100 40
TDC = target frequency of SJC VM = mid-point voltage
3.7.14
SPDIF Timing Parameters
Table 87. SPDIF Timing
All Frequencies Characteristics Symbol Min Max Unit
Table 87 shows the timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF).
SPDIFOUT output (load = 50 pF) * Skew * Transition rising * Transition falling SPDIFOUT output (load = 30 pF) * Skew * Transition rising * Transition falling
--
-- -- -- -- -- --
1.5 24.2 31.3 1.5 13.6 18.0
ns
--
ns
3.7.15
SSI Timing Parameters
This section describes the timing parameters of the SSI module. The connectivity of the serial synchronous interfaces is summarized in Table 88.
Table 88. AUDMUX Port Allocation
Port AUDMUX port 1 AUDMUX port 2 AUDMUX port 3 AUDMUX port 4 AUDMUX port 5 Signal Nomenclature SSI 1 SSI 2 AUD3 AUD4 AUD5 Internal Internal External - AUD3 I/O External - EIM or CSPI1 I/O via IOMUX External - EIM or SD1 I/O via IOMUX Type and Access
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Electrical Characteristics
Table 88. AUDMUX Port Allocation (continued)
Port AUDMUX port 6 AUDMUX port 7 Signal Nomenclature AUD6 SSI 3 Type and Access External - EIM or DISP2 via IOMUX Internal
* *
NOTE The terms WL and BL used in the timing diagrams and tables refer to Word Length (WL) and Byte Length (BL). The SSI timing diagrams use generic signal names wherein the names used in the i.MX51 reference manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC.
SS1 SS2 TXC (Output) SS6 SS8 SS5 SS4 SS3
.
TXFS (bl) (Output) TXFS (wl) (Output)
SS10 SS14 SS15 SS16 SS17 SS18
SS12
TXD (Output) SS43 SS42 RXD (Input) Note: SRXD input in synchronous mode only SS19
Figure 89. SSI Transmitter Internal Clock Timing Diagram
3.7.15.1
SSI Transmitter Timing with Internal Clock
Table 89. SSI Transmitter Timing with Internal Clock
ID
Parameter Internal Clock Operation
Min
Max
Unit
SS1 SS2 SS3
(Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time
81.4 36.0 --
-- -- 6.0
ns ns ns
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Electrical Characteristics
Table 89. SSI Transmitter Timing (continued)with Internal Clock (continued)
ID SS4 SS5 SS6 SS8 SS10 SS12 SS14 SS15 SS16 SS17 SS18 SS19 Parameter (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx/Rx) Internal FS rise time (Tx/Rx) Internal FS fall time (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance STXD rise/fall time Synchronous Internal Clock Operation SS42 SS43 SS52 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling Loading 10.0 0.0 -- -- -- 25.0 ns ns pF Min 36.0 -- -- -- -- -- -- -- -- -- -- -- Max -- 6.0 15.0 15.0 15.0 15.0 6.0 6.0 15.0 15.0 15.0 6.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns
*
* * * *
NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. The terms WL and BL refer to Word Length (WL) and Byte Length (BL). "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
3.7.15.2
SSI Receiver Timing with Internal Clock
SS1 SS2 TXC (Output) SS7 TXFS (bl) (Output) TXFS (wl) (Output) RXD (Input) SS47 SS48 RXC (Output) SS51 SS50 SS49 SS5 SS4 SS3
SS9
SS11
SS13
SS20 SS21
Figure 90. SSI Receiver Internal Clock Timing Diagram Table 90. SSI Receiver Timing with Internal Clock
ID Parameter Internal Clock Operation SS1 SS2 SS3 SS4 SS5 SS7 SS9 SS11 SS13 SS20 SS21 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low Oversampling Clock Operation SS47 Oversampling clock period 15.04 -- ns 81.4 36.0 -- 36.0 -- -- -- -- -- 10.0 0.0 -- -- 6.0 -- 6.0 15.0 15.0 15.0 15.0 -- -- ns ns ns ns ns ns ns ns ns ns ns Min Max Unit
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Electrical Characteristics
Table 90. SSI Receiver Timing with Internal Clock (continued)
ID SS48 SS49 SS50 SS51 Parameter Oversampling clock high period Oversampling clock rise time Oversampling clock low period Oversampling clock fall time Min 6.0 -- 6.0 -- Max -- 3.0 -- 3.0 Unit ns ns ns ns
*
* * * *
NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Byte Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
3.7.15.3
SSI Transmitter Timing with External Clock
SS22 SS23 SS25 SS26
SS24
TXC (Input) SS27 TXFS (bl) (Input) TXFS (wl) (Input) SS37 TXD (Output) SS45 SS44 RXD (Input) Note: SRXD Input in Synchronous mode only SS46 SS38 SS29
SS31
SS33
SS39
Figure 91. SSI Transmitter External Clock Timing Diagram Table 91. SSI Transmitter Timing with External Clock
ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS27 SS29 SS31 SS33 SS37 SS38 SS39 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Tx) CK high to FS (bl) high (Tx) CK high to FS (bl) low (Tx) CK high to FS (wl) high (Tx) CK high to FS (wl) low (Tx) CK high to STXD valid from high impedance (Tx) CK high to STXD high/low (Tx) CK high to STXD high impedance 81.4 36.0 -- 36.0 -- -10.0 10.0 -10.0 10.0 -- -- -- -- -- 6.0 -- 6.0 15.0 -- 15.0 -- 15.0 15.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit
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Electrical Characteristics
Table 91. SSI Transmitter Timing with External Clock (continued)
ID Parameter Synchronous External Clock Operation SS44 SS45 SS46 SRXD setup before (Tx) CK falling SRXD hold after (Tx) CK falling SRXD rise/fall time 10.0 2.0 -- -- -- 6.0 ns ns ns Min Max Unit
*
* * * *
NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Byte Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).
3.7.15.4
SSI Receiver Timing with External Clock
SS22 SS26 SS23 SS25 SS24
TXC (Input) SS28 TXFS (bl) (Input) TXFS (wl) (Input) RXD (Input) SS30
SS32 SS35 SS41 SS40 SS36
SS34
Figure 92. SSI Receiver External Clock Timing Diagram
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Electrical Characteristics
Table 92. SSI Receiver Timing with External Clock
ID Parameter External Clock Operation SS22 SS23 SS24 SS25 SS26 SS28 SS30 SS32 SS34 SS35 SS36 SS40 SS41 (Tx/Rx) CK clock period (Tx/Rx) CK clock high period (Tx/Rx) CK clock rise time (Tx/Rx) CK clock low period (Tx/Rx) CK clock fall time (Rx) CK high to FS (bl) high (Rx) CK high to FS (bl) low (Rx) CK high to FS (wl) high (Rx) CK high to FS (wl) low (Tx/Rx) External FS rise time (Tx/Rx) External FS fall time SRXD setup time before (Rx) CK low SRXD hold time after (Rx) CK low 81.4 36 -- 36 -- -10 10 -10 10 -- -- 10 2 -- -- 6.0 -- 6.0 15.0 -- 15.0 -- 6.0 6.0 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Unit
*
* * * *
NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on Audiomux Pads when SSI is being used for data transfer. "Tx" and "Rx" refer to the Transmit and Receive sections of the SSI. The terms WL and BL refer to Word Length (WL) and Byte Length (BL). For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).
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Electrical Characteristics
3.7.16
UART
Table 93. UART I/O Configuration vs. Mode
DTE Mode DCE Mode Direction Input Output Input Output Output Output Output Input Description RTS from DTE to DCE CTS from DCE to DTE DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE
Table 93 shows the UART I/O configuration based on which mode is enabled.
Port Direction RTS CTS DTR DSR DCD RI TXD_MUX RXD_MUX Output Input Output Input Input Input Input Output Description RTS from DTE to DCE CTS from DCE to DTE DTR from DTE to DCE DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Serial data from DTE to DCE
3.7.17
USBOH3 Parameters
This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip USB PHY parameters see Section 3.7.19, "USB PHY Parameters."
3.7.17.1
USB Serial Interface
In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes: * DAT_SE0 bidirectional, 3-wire mode * DAT_SE0 unidirectional, 6-wire mode * VP_VM bidirectional, 4-wire mode * VP_VM unidirectional, 6-wire mode The USB controller does not support ULPI Serial mode. Only the legacy serial mode is supported.
Table 94. Serial Mode Signal Map for 6-pin FsLs Serial Mode
Signal tx_enable tx_dat tx_se0 int rx_dp rx_dm Maps to data(0) data(1) data(2) data(3) data(4) data(5) Direction In In In Out Out Out Active high transmit enable Transmit differential data on D+/D- Transmit single-ended zero on D+/D- Active high interrupt indication Must be asserted whenever any unmasked interrupt occurs Single-ended receive data from D+ Single-ended receive data from D- Description
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Electrical Characteristics
Table 94. Serial Mode Signal Map for 6-pin FsLs Serial Mode (continued)
Signal rx_rcv Reserved Maps to data(6) data(7) Direction Out Out Description Differential receive data from D+/D- Reserved The PHY must drive this signal low
Table 95. Serial Mode Signal Map for 3-pin FsLs Serial Mode
Signal tx_enable dat se0 int Maps to data(0) data(1) data(2) data(3) Direction In I/O I/O Out Active high transmit enable Transmit differential data on D+/D- when tx_enable is high Receive differential data on D+/D- when tx_enable is low Transmit single-ended zero on D+/D- when tx_enable is high Receive single-ended zero on D+/D- when tx_enable is low Active high interrupt indication Must be asserted whenever any unmasked interrupt occurs Description
3.7.17.1.1
USB DAT_SE0 Bi-Directional Mode
Table 96. Signal Definitions--DAT_SE0 Bi-Directional Mode
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM
Direction Out Out In Out In
Signal Description Transmit enable, active low TX data when USB_TXOE_B is low Differential RX data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low SE0 RX indicator when USB_TXOE_B is high
Transmit USB_TXOE_B
US3
USB_DAT_VP
USB_SE0_VM
US1
US4 US2
Figure 93. USB Transmit Waveform in DAT_SE0 Bi-Directional Mode
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Electrical Characteristics
Receive USB_TXOE_B USB_DAT_VP USB_SE0_VM
US7
US8
USB_SE0_VM
Figure 94. USB Receive Waveform in DAT_SE0 Bi-Directional Mode Table 97. Definitions of USB Receive Waveform in DAT_SE0 Bi-Directional Mode
ID US1 US2 US3 US4 US7 US8 Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle RX Rise/Fall Time RX Rise/Fall Time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_DAT_VP USB_SE0_VM Direction Out Out Out Out In In Min - - - 49.0 - - Max 5.0 5.0 5.0 51.0 3.0 3.0 Unit ns ns ns % ns ns Conditions/ Reference Signal 50 pF 50 pF 50 pF - 35 pF 35 pF
3.7.17.1.2
USB DAT_SE0 Unidirectional Mode
Table 98. Signal Definitions--DAT_SE0 Unidirectional Mode
Name USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV
Direction Out Out Out In In In Transmit enable, active low
Signal Description
TX data when USB_TXOE_B is low SE0 drive when USB_TXOE_B is low Buffered data on DP when USB_TXOE_B is high Buffered data on DM when USB_TXOE_B is high Differential RX data when USB_TXOE_B is high
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Electrical Characteristics
Transmit USB_TXOE_B
US11
USB_DAT_VP
USB_SE0_VM
US9
US12 US10
Figure 95. USB Transmit Waveform in DAT_SE0 Uni-directional Mode
Receive USB_TXOE_B
USB_DAT_VP USB_RCV
US16 US15/US17 USB_SE0_VM
Figure 96. USB Receive Waveform in DAT_SE0 Uni-directional Mode Table 99. USB Port Timing Specification in DAT_SE0 Uni-directional Mode
ID US9 Parameter TX Rise/Fall Time Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_VP1 USB_VM1 USB_RCV Signal Source Out Out Out Out In In In Min - - - 49.0 - - - Max 5.0 5.0 5.0 51.0 3.0 3.0 3.0 Unit ns ns ns % ns ns ns Condition/ Reference Signal 50 pF 50 pF 50 pF - 35 pF 35 pF 35 pF
US10 TX Rise/Fall Time US11 TX Rise/Fall Time US12 TX Duty Cycle US15 RX Rise/Fall Time US16 RX Rise/Fall Time US17 RX Rise/Fall Time
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Electrical Characteristics
3.7.17.1.3
USB VP_VM Bi-Directional Mode
Table 100. Signal Definitions--VP_VM Bi-Directional Mode
Name Direction Out Out (Tx) In (Rx) Out (Tx) In (Rx) In Signal Description Transmit enable, active low TX VP data when USB_TXOE_B is low RX VP data when USB_TXOE_B is high TX VM data when USB_TXOE_B low RX VM data when USB_TXOE_B high Differential RX data
USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_RCV
Transmit
US20 USB_TXOE_B
USB_DAT_VP
USB_SE0_VM
US18 US21 US19
US22
US22
Figure 97. USB Transmit Waveform in VP_VM Bi-Directional Mode
Receive
US26 USB_DAT_VP
USB_SE0_VM US28 US27
USB_RCV
US29
Figure 98. USB Receive Waveform in VP_VM Bi-Directional Mode
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Electrical Characteristics
Table 101. USB Port Timing Specification in VP_VM Bi-directional Mode
ID Parameter Signal Name USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_SE0_VM USB_DAT_VP USB_RCV Direction Out Out Out Out Out In In Out Out Min -- -- -- 49.0 -3.0 -- -- -4.0 -6.0 Max 5.0 5.0 5.0 51.0 3.0 3.0 3.0 4.0 2.0 Unit ns ns ns % ns ns ns ns ns Condition / Reference Signal 50 pF 50 pF 50 pF -- USB_DAT_VP 35 pF 35 pF USB_SE0_VM USB_DAT_VP
US18 TX Rise/Fall Time US19 TX Rise/Fall Time US20 TX Rise/Fall Time US21 TX Duty Cycle US22 TX Overlap US26 RX Rise/Fall Time US27 RX Rise/Fall Time US28 RX Skew US29 RX Skew
3.7.17.1.4
USB VP_VM Uni-Directional Mode
Table 102. USB Signal Definitions--VP_VM Uni-Directional Mode
Name Direction Out Out Out In In In Signal Description Transmit enable, active low TX VP data when USB_TXOE_B is low TX VM data when USB_TXOE_B is low RX VP data when USB_TXOE_B is high RX VM data when USB_TXOE_B is high Differential RX data
USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_RCV Transmit
US32 USB_TXOE_B USB_DAT_VP
USB_SE0_VM US30 US33 US31
US34
US34
Figure 99. USB Transmit Waveform in VP_VM Unidirectional Mode
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Electrical Characteristics
Receive
USB_TXOE_B
USB_VP1
US38
USB_VM1 US40
USB_RCV US39
US41
Figure 100. USB Receive Waveform in VP_VM Unidirectional Mode Table 103. USB Timing Specification in VP_VM Unidirectional Mode
ID US30 US31 US32 US33 US34 US38 US39 US40 US41 Parameter TX Rise/Fall Time TX Rise/Fall Time TX Rise/Fall Time TX Duty Cycle TX Overlap RX Rise/Fall Time RX Rise/Fall Time RX Skew RX Skew Signal USB_DAT_VP USB_SE0_VM USB_TXOE_B USB_DAT_VP USB_SE0_VM USB_VP1 USB_VM1 USB_VP1 USB_RCV Direction Out Out Out Out Out In In Out Out Min -- -- -- 49.0 -3.0 -- -- -4.0 -6.0 Max 5.0 5.0 5.0 51.0 3.0 3.0 3.0 4.0 2.0 Unit ns ns ns % ns ns ns ns ns Conditions / Reference Signal 50 pF 50 pF 50 pF -- USB_DAT_VP 35 pF 35 pF USB_SE0_VM USB_DAT_VP
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Electrical Characteristics
3.7.18
USB Parallel Interface Timing
Table 104. Signal Definitions--Parallel Interface (Normal ULPI)
Name USB_Clk Direction In I/O In Out In Signal Description Interface clock. All interface signals are synchronous to Clock. Bi-directional data bus, driven low by the link during idle. Bus ownership is determined by Dir. Direction. Control the direction of the Data bus. Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus. Next. The PHY asserts this signal to throttle the data.
Electrical and timing specifications of Parallel Interface are presented in the subsequent sections.
USB_Data[7:0] USB_Dir USB_Stp USB_Nxt
USB_Clk
US15 USB_Dir/Nxt US15 USB_Data
US16
US16
US17 USB_Stp
US17
Figure 101. USB Transmit/Receive Waveform in Parallel Mode Table 105. USB Timing Specification for ULPI Parallel Mode
ID US15 US16 US17 Parameter Setup Time (Dir, Nxt in, Data in) Hold Time (Dir, Nxt in, Data in) Output delay Time (Stp out, Data out) Min 6 0 -- Max -- -- 9 Unit ns ns ns Conditions / Reference Signal 10 pF 10 pF 10 pF
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Electrical Characteristics
3.7.19
3.7.19.1
USB PHY Parameters
USB PHY AC Parameters
Table 106. USB PHY AC Timing Parameters
Parameter trise
Conditions 1.5Mbps 12Mbps 480Mbps 1.5Mbps 12Mbps 480Mbps 1.5Mbps 12Mbps 480Mbps
Min 75 4 0.5 75 4 0.5 --
Typ --
Max 300 20 300 20 10 1 0.2
Unit ns
tfall
--
ns
Jitter
--
ns
3.7.19.2
USB PHY Additional Electrical Parameters
Table 107. Additional Electrical Characteristics for USB PHY
Parameter Conditions HS Mode LS/FS Mode LS Mode FS Mode <160 MHz <1.2 MHz >1.2 MHz All conditions Min -0.05 0.8 1.3 1.3 -50 -10 -50 -50 Typ -- -- 0 0 0 0 Max 0.5 2.5 2 2 50 10 50 50 Unit V V mV mV mV
Vcm DC (dc level measured at receiver connector) Crossover Voltage Power supply ripple noise (analog 3.3 V) Power supply ripple noise (analog 2.5 V) Power supply ripple noise (Digital 1.2)
3.7.19.3
USB PHY System Clocking (SYSCLK)
Table 108. USB PHY System Clocking Parameters
Parameter Clock deviation Rise/fall time Jitter (peak-peak) Jitter (peak-peak) Duty-cycle
Conditions -- -- <1.2 MHz >1.2 MHz --
Min -150 -- 0 0 40
Typ -- -- -- -- --
Max 150 200 50 100 60
Unit ppm ps ps ps %
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Package Information and Contact Assignments
3.7.19.4
USB PHY Voltage Thresholds
Table 109. VBUS Comparators Thresholds
Parameter Conditions -- -- -- -- Min 0.8 0.8 0.2 4.4 Typ 1.4 1.4 0.45 4.6 Max 2.0 4.0 0.8 4.75 Unit V V V V
A-Device Session Valid B-Device Session Valid B-Device Session End VBUS Valid Comparator Threshold1
1
For VBUS maximum rating, see Table 6 on page 14
4
Package Information and Contact Assignments
This section includes the contact assignment information and mechanical package drawing.
4.1
19 x 19 mm Package Information
This section contains the outline drawing, signal assignment map, ground/power/reference ID (by ball grid location) for the 19 x 19 mm, 0.8 mm pitch package.
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4.1.1
BGA--Case 2017, 19 x 19 mm, 0.8 mm Pitch
Figure 102. 19 x 19 mm Package: Case 2017-01--0.8 mm Pitch
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4.1.1.1
1 2
19 x 19 mm Package Drawing Notes
The following notes apply to Figure 102.
All dimensions in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to Datum A. 4 Datum A, the seating plane, is determined by the spherical crowns of the solder balls. 5 Parallelism measurement shall exclude any effect of mark on top surface of package.
4.1.2
19 x 19 mm Signal Assignments, Power Rails, and I/O
Table 110 shows the device connection list and Table 111 displays an alpha-sorted list of the signal assignments including associated power supplies.
4.1.2.1
19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Table 110 shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name.
Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments
Contact Name AHVDDRGB AHVSSRGB GND Y18, AA18 Y19, AA19 A1 , A23, G5, H9, J8, J9, J10, J12, J13, J14, K8, K9, K10, K11, K12, K13, K14, L8, L9, L10, L11,L12, L13, L14, M9, M10, M11, M12, M13, M14, M15, N8, N9, N10, N11, N12, N13, N14, N15, N16, P8, P9, P10, P11, P12, P13, P14, P15, R8, R9, R10, R11,R12, R13, R14, R15, R16, T5, T16, AC1, AC21, AC23 U7 U17 T7 V18 V17 T15 L16 U8, U9, U10, U11, U12, V7 H6, J6, K6, L6, M6, N6, P6, R6, T6 M16 M18 N18 M17 T14 Contact Assignment
GND_ANA_PLL_A GND_ANA_PLL_B GND_DIG_PLL_A GND_DIG_PLL_B NGND_OSC NGND_TV_BACK NGND_USBPHY NVCC_EMI NVCC_EMI_DRAM NVCC_HS10 NVCC_HS4_1 NVCC_HS4_2 NVCC_HS6 NVCC_I2C
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Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)
Contact Name NVCC_IPU2 NVCC_IPU4 NVCC_IPU5 NVCC_IPU6 NVCC_IPU7 NVCC_IPU8 NVCC_IPU9 NVCC_NANDF_A NVCC_NANDF_B NVCC_NANDF_C NVCC_OSC NVCC_PER3 NVCC_PER5 NVCC_PER8 NVCC_PER9 NVCC_PER10 NVCC_PER11 NVCC_PER12 NVCC_PER13 NVCC_PER14 NVCC_PER15 NVCC_PER17 NVCC_SRTC_POW NVCC_TV_BACK NVCC_USBPHY RREFEXT SGND SVCC SVDDGP TVDAC_DHVDD VBUS VCC VDD_ANA_PLL_A T18 G16 H17 J17 K17 P18 R18 E6, F5 G9 G10 W17 U18 G15 H16 H10 H11 G11 G12 G13 U13 H15 G14 U14 U16 L17 K19 J11 H14 F13 V16 K20 H13, J15, J16, K15, K16, L7, L15, M7, N7, N17, P7, P17, R17, T8, T9, T10, T11, T12, T17 V6 Contact Assignment
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Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)
Contact Name VDD_ANA_PLL_B VDD_DIG_PLL_A VDD_DIG_PLL_B VDD_FUSE VDDA VDDA33 VDDGP VREFOUT VREF VREG W19 U6 W18 R7 G8, H8, H12, M8, P16, T13 L18 F6, F7, F8, F9, F10, F11, F12, G6, G7, H7, J7, K7 U15 R5 K21 Contact Assignment
4.1.2.2
19 x 19 mm, Signal Assignments, Power Rails, and I/O
Table 111 displays an alpha-sorted list of the signal assignments including power rails.
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O
Contact Name AUD3_BB_CK AUD3_BB_FS AUD3_BB_RXD AUD3_BB_TXD BOOT_MODE0 BOOT_MODE1 CKIH1 CKIH2 CKIL CLK_SS COMP CSI1_D10 CSI1_D11 CSI1_D12 CSI1_D13 CSI1_D14 Contact Assignment C8 A9 B9 E9 AB21 AB22 V19 AA20 Y16 AA21 Y17 R22 R23 P22 P23 M20 Power Rail NVCC_PER9 NVCC_PER9 NVCC_PER9 NVCC_PER9 NVCC_PER3 NVCC_PER3 NVCC_PER3 NVCC_PER3 NVCC_SRTC_POW NVCC_PER3 AHVDDRGB NVCC_HS10 NVCC_HS10 NVCC_HS10 NVCC_HS10 NVCC_HS10 I/O Buffer Type GPIO GPIO GPIO GPIO LVIO LVIO Analog Analog GPIO LVIO Analog HSGPIO HSGPIO HSGPIO HSGPIO HSGPIO Direction after Reset1 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Configuraton after Reset1 Keeper Keeper Keeper Keeper 100 k pull-up 100 k pull-up Analog Analog Standard CMOS 100 k pull-up Analog Keeper Keeper Keeper Keeper Keeper
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name CSI1_D15 CSI1_D16 CSI1_D17 CSI1_D18 CSI1_D19 CSI1_D8 CSI1_D9 CSI1_HSYNC CSI1_MCLK CSI1_PIXCLK CSI1_VSYNC CSI2_D12 CSI2_D13 CSI2_D14 CSI2_D15 CSI2_D16 CSI2_D17 CSI2_D18 CSI2_D19 CSI2_HSYNC CSI2_PIXCLK CSI2_VSYNC CSPI1_MISO CSPI1_MOSI CSPI1_RDY CSPI1_SCLK CSPI1_SS0 CSPI1_SS1 DI_GP1 DI_GP2 DI_GP3 DI_GP4 Contact Assignment M21 N22 N23 M22 M23 E18 A21 A20 B20 F18 G18 B8 C7 L20 L21 L22 L23 D9 A8 C18 E19 F19 C10 D10 C9 A10 E10 B10 H21 J19 H22 J22 Power Rail NVCC_HS10 NVCC_HS10 NVCC_HS10 NVCC_HS10 NVCC_HS10 NVCC_PER8 NVCC_PER8 NVCC_PER8 NVCC_PER8 NVCC_PER8 NVCC_PER8 NVCC_PER9 NVCC_PER9 NVCC_HS4_1 NVCC_HS4_1 NVCC_HS4_1 NVCC_HS4_1 NVCC_PER9 NVCC_PER9 NVCC_PER8 NVCC_PER8 NVCC_PER8 NVCC_PER10 NVCC_PER10 NVCC_PER10 NVCC_PER10 NVCC_PER10 NVCC_PER10 NVCC_IPU6 NVCC_IPU6 NVCC_IPU7 NVCC_IPU7 I/O Buffer Type HSGPIO HSGPIO HSGPIO HSGPIO HSGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HSGPIO HSGPIO HSGPIO HSGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Direction after Reset1 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Configuraton after Reset1 Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper 100 k pull-up 100 k pull-up Keeper 100 k pull-up 100 k pull-up 100 k pull-up Keeper Keeper 100 k pull-up 100 k pull-up
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name DI1_D0_CS DI1_D1_CS DI1_DISP_CLK DI1_PIN11 DI1_PIN12 DI1_PIN13 DI1_PIN15 DI1_PIN2 DI1_PIN3 DI2_DISP_CLK DI2_PIN2 DI2_PIN3 DI2_PIN4 DISP1_DAT0 DISP1_DAT1 DISP1_DAT102 DISP1_DAT112 DISP1_DAT122 DISP1_DAT132 DISP1_DAT142 DISP1_DAT152 DISP1_DAT162 DISP1_DAT172 DISP1_DAT182 DISP1_DAT192 DISP1_DAT2 DISP1_DAT202 DISP1_DAT212 DISP1_DAT222 DISP1_DAT232 DISP1_DAT3 DISP1_DAT4 Contact Assignment U21 AB23 J18 Y22 AA22 T20 H20 G23 G22 J21 J20 K18 H23 N20 N21 D22 D23 E21 F20 E22 G19 E23 F21 G20 H18 U22 F23 H19 F22 G21 U23 T22 Power Rail NVCC_IPU2 NVCC_IPU2 NVCC_IPU6 NVCC_IPU2 NVCC_IPU2 NVCC_IPU2 NVCC_IPU6 NVCC_IPU6 NVCC_IPU6 NVCC_IPU7 NVCC_IPU7 NVCC_IPU7 NVCC_IPU7 NVCC_HS6 NVCC_HS6 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU5 NVCC_IPU5 NVCC_IPU5 NVCC_IPU5 NVCC_HS6 NVCC_IPU5 NVCC_IPU5 NVCC_IPU5 NVCC_IPU5 NVCC_HS6 NVCC_HS6 I/O Buffer Type GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HSGPIO HSGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HSGPIO GPIO GPIO GPIO GPIO HSGPIO HSGPIO Direction after Reset1 Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Configuraton after Reset1 Low Low Low Low Low High High High High High High High Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name DISP1_DAT5 DISP1_DAT62 DISP1_DAT72 DISP1_DAT82 DISP1_DAT92 DISP2_DAT0 DISP2_DAT1 DISP2_DAT10 DISP2_DAT11 DISP2_DAT12 DISP2_DAT13 DISP2_DAT14 DISP2_DAT15 DISP2_DAT2 DISP2_DAT3 DISP2_DAT4 DISP2_DAT5 DISP2_DAT6 DISP2_DAT7 DISP2_DAT8 DISP2_DAT9 DISPB2_SER_CLK DISPB2_SER_DIN DISPB2_SER_DIO DISPB2_SER_RS DN DP DRAM_A0 DRAM_A1 DRAM_A10 DRAM_A11 DRAM_A12 Contact Assignment T23 C22 C23 D21 E20 R21 M19 W22 R19 Y23 T19 AA23 T21 P20 P21 V22 V23 N19 W23 P19 R20 AC22 U19 V21 W21 K22 K23 AB1 AA2 V2 U4 U2 Power Rail NVCC_HS6 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU4 NVCC_IPU8 NVCC_IPU8 NVCC_IPU9 NVCC_IPU9 NVCC_IPU9 NVCC_IPU9 NVCC_IPU9 NVCC_IPU9 NVCC_HS4_2 NVCC_HS4_2 NVCC_HS4_2 NVCC_HS4_2 NVCC_IPU8 NVCC_IPU8 NVCC_IPU9 NVCC_IPU9 NVCC_IPU2 NVCC_IPU2 NVCC_IPU2 NVCC_IPU2 VDDA33 VDDA33 NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM I/O Buffer Type HSGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO HSGPIO HSGPIO HSGPIO HSGPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Analog Analog DDR2 DDR2 DDR2 DDR2 DDR2 Direction after Reset1 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Output Output Output Output Output Output Output Output Configuraton after Reset1 Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper High 100 k pull-up 100 k pull-up High - - High High High High High
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name DRAM_A13 DRAM_A14 DRAM_A2 DRAM_A3 DRAM_A4 DRAM_A5 DRAM_A6 DRAM_A7 DRAM_A8 DRAM_A9 DRAM_CAS DRAM_CS0 DRAM_CS1 DRAM_D0 DRAM_D1 DRAM_D10 DRAM_D11 DRAM_D12 DRAM_D13 DRAM_D14 DRAM_D15 DRAM_D16 DRAM_D17 DRAM_D18 DRAM_D19 DRAM_D2 DRAM_D20 DRAM_D21 DRAM_D22 DRAM_D23 DRAM_D24 DRAM_D25 Contact Assignment U1 T2 AA3 V5 W4 Y2 W3 Y1 W2 V3 V4 Y4 Y3 T1 R3 M3 M4 M1 M5 L5 L4 L3 L2 L1 K1 R2 K3 K4 J3 J4 K5 H1 Power Rail NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM I/O Buffer Type DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 Direction after Reset1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Configuraton after Reset1 High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name DRAM_D26 DRAM_D27 DRAM_D28 DRAM_D29 DRAM_D3 DRAM_D30 DRAM_D31 DRAM_D4 DRAM_D5 DRAM_D6 DRAM_D7 DRAM_D8 DRAM_D9 DRAM_DQM0 DRAM_DQM1 DRAM_DQM2 DRAM_DQM3 DRAM_RAS DRAM_SDCKE0 DRAM_SDCKE1 DRAM_SDCLK DRAM_SDCLK_B DRAM_SDQS0 DRAM_SDQS0_B DRAM_SDQS1 DRAM_SDQS1_B DRAM_SDQS2 DRAM_SDQS2_B DRAM_SDQS3 DRAM_SDQS3_B DRAM_SDWE EIM_A162 Contact Assignment H2 J5 G1 G2 R1 G3 G4 R4 P5 P4 N5 N2 N1 P3 M2 K2 H5 W1 AA1 W5 T3 T4 P2 P1 N4 N3 J1 J2 H3 H4 U5 AA9 Power Rail NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI I/O Buffer Type DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2 DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2CLK DDR2 GPIO Direction after Reset1 Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Configuraton after Reset1 High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High High 100 k pull-up
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Package Information and Contact Assignments
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name EIM_A172 EIM_A182 EIM_A192 EIM_A202 EIM_A212 EIM_A22 EIM_A232 EIM_A24 EIM_A25 EIM_A26 EIM_A27 EIM_BCLK EIM_CRE EIM_CS0 EIM_CS1 EIM_CS2 EIM_CS3 EIM_CS4 EIM_CS5 EIM_D16 EIM_D17 EIM_D18 EIM_D19 EIM_D20 EIM_D21 EIM_D22 EIM_D23 EIM_D24 EIM_D25 EIM_D26 EIM_D27 EIM_D28 Contact Assignment AB9 AC8 AA8 AB8 AC7 AB7 AC6 AC5 AB6 AC4 AB5 AA4 AB2 W6 Y6 Y7 AC3 AA6 AA5 AC12 W10 AA11 Y10 AB11 W9 AC11 V8 AA10 Y9 AB10 W8 AC10 Power Rail NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI I/O Buffer Type GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Direction after Reset1 Input Input Input Input Input Output Input Input Input Input Input Input Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Configuraton after Reset1 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up High 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up Keeper Keeper High High High Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name EIM_D29 EIM_D30 EIM_D31 EIM_DA0 EIM_DA1 EIM_DA10 EIM_DA11 EIM_DA12 EIM_DA13 EIM_DA14 EIM_DA15 EIM_DA2 EIM_DA3 EIM_DA4 EIM_DA5 EIM_DA6 EIM_DA7 EIM_DA8 EIM_DA9 EIM_DTACK EIM_EB0 EIM_EB1 EIM_EB2 EIM_EB3 EIM_LBA EIM_OE EIM_RW EIM_SDBA0 EIM_SDBA1 EIM_SDBA2 EIM_SDODT0 EIM_SDODT1 Contact Assignment Y8 AC9 W7 AC15 V13 AC13 V11 AA12 W11 AB12 Y11 AA14 AB14 AC14 Y13 AA13 W13 AB13 Y12 Y5 V12 W12 V10 V9 AC2 AA7 AB3 V1 U3 F1 F3 F2 Power Rail NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM I/O Buffer Type GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO DDR2 DDR2 DDR2 DDR2 DDR2 Direction after Reset1 Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Input Input Output Output Output Output Output Output Output Output Configuraton after Reset1 Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper 100 k pull-up High High Keeper Keeper High High High High High High High High
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Package Information and Contact Assignments
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name EIM_WAIT EXTAL FASTR_ANA FASTR_DIG GPANAIO GPIO_NAND GPIO1_0 GPIO1_1 GPIO1_2 GPIO1_3 GPIO1_4 GPIO1_5 GPIO1_6 GPIO1_7 GPIO1_8 GPIO1_9 I2C1_CLK I2C1_DAT ID IOB IOB_BACK IOG IOG_BACK IOR IOR_BACK JTAG_DE_B JTAG_MOD JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS Contact Assignment AB4 AB20 W20 Y20 J23 D5 B21 D20 A22 D18 B22 D19 C19 B23 C21 C20 W15 AB16 L19 AC19 AB19 AC18 AB18 AC17 AB17 AB15 V14 V15 Y14 AA15 AC16 Power Rail NVCC_EMI NVCC_OSC NVCC_PER3 NVCC_PER3 NVCC_USBPHY NVCC_NANDF_A NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_PER5 NVCC_I2C NVCC_I2C NVCC_USBPHY AHVDDRGB -- AHVDDRGB -- AHVDDRGB -- NVCC_PER14 NVCC_PER14 NVCC_PER14 NVCC_PER14 NVCC_PER14 NVCC_PER14 I/O Buffer Type GPIO Analog - - Analog UHVIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO I2CIO I2CIO Analog Analog Analog Analog Analog Analog Analog GPIO GPIO GPIO GPIO GPIO GPIO Direction after Reset1 Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Output Input/Open-drain output Input Input Input 3-state output Input Configuraton after Reset1 100 k pull-up - - - - 100 k pull-up Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper 47 k pull-up 47 k pull-up Pull-up -- -- -- -- -- -- 47 k pull-up 100 k pull-down 100 k pull-down 47 k pull-up Keeper 47 k pull-up
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Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name JTAG_TRSTB KEY_COL0 KEY_COL1 KEY_COL2 KEY_COL33 KEY_COL43 KEY_COL53 KEY_ROW0 KEY_ROW1 KEY_ROW2 KEY_ROW3 NANDF_ALE NANDF_CLE NANDF_CS0 NANDF_CS1 NANDF_CS2 NANDF_CS3 NANDF_CS4 NANDF_CS5 NANDF_CS6 NANDF_CS7 NANDF_D0 NANDF_D1 NANDF_D10 NANDF_D11 NANDF_D12 NANDF_D13 NANDF_D14 NANDF_D15 NANDF_D2 NANDF_D3 NANDF_D4 Contact Assignment W14 E15 A16 D15 B17 F16 C16 D14 B16 F15 C15 E3 F4 C3 C2 E4 B1 B2 A2 E5 C4 A7 E8 B5 D7 C5 A3 B4 D6 A6 D8 B7 Power Rail NVCC_PER14 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_PER13 NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_C NVCC_NANDF_C NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_C NVCC_NANDF_C NVCC_NANDF_C I/O Buffer Type GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO Direction after Reset1 Input Input Input Input Output Output Output Input Input Input Input Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Configuraton after Reset1 47 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up High Low Low 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up High High High High High High Low Low Low Low Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper
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Package Information and Contact Assignments
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name NANDF_D5 NANDF_D6 NANDF_D7 NANDF_D8 NANDF_D9 NANDF_RB0 NANDF_RB1 NANDF_RB2 NANDF_RB3 NANDF_RDY_INT NANDF_RE_B NANDF_WE_B NANDF_WP_B OWIRE_LINE PMIC_INT_REQ PMIC_ON_REQ PMIC_RDY PMIC_STBY_REQ POR_B RESET_IN_B SD1_CLK SD1_CMD SD1_DATA0 SD1_DATA1 SD1_DATA2 SD1_DATA3 SD2_CLK SD2_CMD SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_DATA3 Contact Assignment A5 B6 C6 A4 E7 D2 D4 D3 C1 B3 E2 E1 D1 E14 AA16 W16 AA17 Y15 U20 Y21 A17 E16 D16 A18 F17 A19 B18 G17 E17 B19 D17 C17 Power Rail NVCC_NANDF_C NVCC_NANDF_C NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_B NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_B NVCC_NANDF_A NVCC_NANDF_A NVCC_NANDF_A NVCC_PER12 NVCC_SRTC_POW NVCC_SRTC_POW NVCC_SRTC_POW NVCC_SRTC_POW NVCC_PER3 NVCC_PER3 NVCC_PER15 NVCC_PER15 NVCC_PER15 NVCC_PER15 NVCC_PER15 NVCC_PER15 NVCC_PER17 NVCC_PER17 NVCC_PER17 NVCC_PER17 NVCC_PER17 NVCC_PER17 I/O Buffer Type UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO GPIO GPIO GPIO GPIO GPIO LVIO LVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO UHVIO Direction after Reset1 Input Input Input Input Input Input Input Input Input Input Output Output Output Input Input Input Input Input Input Input Output Input Input Input Input Input Output Input Input Input Input Input Configuraton after Reset1 Keeper Keeper Keeper Keeper Keeper 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up -- -- -- 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up -- 47 k pull-up 47 k pull-up 47 k pull-up 47 k pull-up 360 k pull-down -- 47 k pull-up 47 k pull-up 47 k pull-up 47 k pull-up 360 k pull-down
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Package Information and Contact Assignments
Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Contact Name STR TEST_MODE UART1_CTS UART1_RTS UART1_RXD UART1_TXD UART2_RXD UART2_TXD UART3_RXD UART3_TXD USBH1_CLK USBH1_DATA0 USBH1_DATA1 USBH1_DATA2 USBH1_DATA3 USBH1_DATA4 USBH1_DATA5 USBH1_DATA6 USBH1_DATA7 USBH1_DIR USBH1_NXT USBH1_STP XTAL
1 2
Contact Assignment A15 V20 B14 D13 E13 A13 A14 C14 F14 B15 D11 E12 A11 B12 C12 D12 A12 B13 C13 B11 C11 E11 AC20
Power Rail NVCC_PER12 NVCC_PER3 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVVCC_PER12 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_PER11 NVCC_OSC
I/O Buffer Type
Direction after Reset1 --
Configuraton after Reset1 -- 100 k pull-down 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper --
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Analog
Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
The state immediately after reset and before ROM firmware or software has executed. During power-on reset this port acts as input for fuse override signal. See Table 112 on page 151 for details 3 During power-on reset this port acts as output for diagnostic signal. See Table 112 on page 151 for details
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 150 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package Information and Contact Assignments
4.1.2.3
Fuse Override Considerations
Table 112. Fuse Override Contacts
Table 112 lists the contacts that can be overridden with fuse settings.
Contact name DISP1_DAT10 DISP1_DAT11 DISP1_DAT12 DISP1_DAT13 DISP1_DAT14 DISP1_DAT15 DISP1_DAT16 DISP1_DAT17 DISP1_DAT18 DISP1_DAT19 DISP1_DAT20 DISP1_DAT21 DISP1_DAT22 DISP1_DAT23 DISP1_DAT6 DISP1_DAT7 DISP1_DAT8 DISP1_DAT9 EIM_A16 EIM_A17 EIM_A18 EIM_A19 EIM_A20 EIM_A21 EIM_A23 KEY_COL3
Direction After Reset Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output
Configuration After Reset Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up 100 k pull-up High
Signal Configuration1 BT_SPARE_SIZE BT_LPB_FREQ[2] BT_MLC_SEL BT_MEM_CTL[0] BT_MEM_CTL[1] BT_BUS_WIDTH BT_PAGE_SIZE[0] BT_PAGE_SIZE[1] BT_WEIM_MUXED[0] BT_WEIM_MUXED[1] BT_MEM_TYPE[0] BT_MEM_TYPE[1] BT_LPB_FREQ[0] BT_LPB_FREQ[1] BT_USB_SRC BT_EEPROM_CFG BT_SRC[0] BT_SRC[1] OSC_FREQ_SEL[0] OSC_FREQ_SEL[1] BT_LPB[0] BT_LPB[1] BT_UART_SRC[0] BT_UART_SRC[1] No longer used; formerly BT_HPN_EN. Output for diagnostic signal INT_BOOT during power-on reset
External Termination for Fuse Override 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-up or pull-down 4.7 k pull-down or none for high level2 4.7 k pull-down or none for high level2 4.7 k pull-down or none for high level2 4.7 k pull-down or none for high level2 4.7 k pull-down or none for high level2 4.7 k pull-down or none for high level2 none
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 151
Package Information and Contact Assignments
Table 112. Fuse Override Contacts (continued)
Contact name KEY_COL4 Direction After Reset Output Configuration After Reset Low Signal Configuration1 Output for diagnostic signal ANY_PU_RST during power-on reset Output for diagnostic signal JTAG_ACT during power-on reset External Termination for Fuse Override
KEY_COL5
Output
Low
1
Signal Configuration as Fuse Override Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration is controlled by fuses. 2 Consider using an external 68 k pull-up if system constraints indicate that the on-chip 100 k pull-up is too weak.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 152 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Package Information and Contact Assignments
C D A B E F
23 22 21 20 19 18 17 16
GND GPIO1_2 CSI1_D9 CSI1_HSYNC SD1_DATA3 SD1_DATA1 SD1_CLK KEY_COL1 STR UART2_RXD UART1_TXD USBH1_DATA5 USBH1_DATA1 CSPI1_SCLK AUD3_BB_FS CSI2_D19 NANDF_D0 NANDF_D2 NANDF_D5 NANDF_D8 NANDF_D13 NANDF_CS5 GND
A
GPIO1_7 GPIO1_4 GPIO1_0 CSI1_MCLK SD2_DATA1 SD2_CLK KEY_COL3 KEY_ROW1 UART3_TXD UART1_CTS USBH1_DATA6 USBH1_DATA2 USBH1_DIR CSPI1_SS1 AUD3_BB_RXD CSI2_D12 NANDF_D4 NANDF_D6 NANDF_D10 NANDF_D14 NANDF_RDY_INT NANDF_CS4 NANDF_CS3
B
DISP1_DAT7 DISP1_DAT6 GPIO1_8 GPIO1_9 GPIO1_6 CSI2_HSYNC SD2_DATA3 KEY_COL5 KEY_ROW3 UART2_TXD USBH1_DATA7
DISP1_DAT11 DISP1_DAT10 DISP1_DAT8 GPIO1_1 GPIO1_5 GPIO1_3 SD2_DATA2 SD1_DATA0 KEY_COL2 KEY_ROW0 UART1_RTS
DISP1_DAT16 DISP1_DAT14 DISP1_DAT12 DISP1_DAT9 CSI2_PIXCLK CSI1_D8 SD2_DATA0 SD1_CMD KEY_COL0 OWIRE_LINE UART1_RXD USBH1_DATA0 USBH1_STP CSPI1_SS0 AUD3_BB_TXD NANDF_D1 NANDF_D9 NVCC_NANDF_A NANDF_CS6 NANDF_CS2 NANDF_ALE NANDF_RE_B NANDF_WE_B
E
DISP1_DAT20 DISP1_DAT22 DISP1_DAT17 DISP1_DAT13 CSI2_VSYNC CSI1_PIXCLK SD1_DATA2 KEY_COL4 KEY_ROW2 UART3_RXD SVDDGP VDDGP VDDGP VDDGP VDDGP VDDGP VDDGP VDDGP NVCC_NANDF_A NANDF_CLE EIM_SDODT0 EIM_SDODT1 EIM_SDBA2
F
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Table 113. 19 x 19 mm, 0.8 Pitch Ball Map
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
USBH1_DATA3 USBH1_DATA4 USBH1_NXT CSPI1_MISO CSPI1_RDY AUD3_BB_CK CSI2_D13 NANDF_D7 NANDF_D12 NANDF_CS7 NANDF_CS0 NANDF_CS1 NANDF_RB3
C
USBH1_CLK CSPI1_MOSI CSI2_D18 NANDF_D3 NANDF_D11 NANDF_D15 GPIO_NAND NANDF_RB1 NANDF_RB2 NANDF_RB0 NANDF_WP_B
D
19 x 19 mm, 0.8 Pitch Ball Map 4.2
Table 113 shows the 19 x 19 mm, 0.8 pitch ball map.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 153
Package Information and Contact Assignments
G H K L J
23 22 21 20 19 18 17
DI1_PIN2 DI1_PIN3 DISP1_DAT23 DISP1_DAT18 DISP1_DAT15 CSI1_VSYNC SD2_CMD NVCC_IPU4 NVCC_PER5 NVCC_PER17 NVCC_PER13 NVCC_PER12 NVCC_PER11 NVCC_NANDF_C NVCC_NANDF_B VDDA VDDGP VDDGP GND DRAM_D31 DRAM_D30 DRAM_D29 DRAM_D28
G
DI2_PIN4 DI_GP3 DI_GP1 DI1_PIN15 DISP1_DAT21 DISP1_DAT19 NVCC_IPU5 NVCC_PER8 NVCC_PER15 SVCC VCC VDDA NVCC_PER10 NVCC_PER9 GND VDDA VDDGP
GPANAIO DI_GP4 DI2_DISP_CLK DI2_PIN2 DI_GP2 DI1_DISP_CLK NVCC_IPU6 VCC VCC GND GND GND SGND GND GND GND VDDGP
DP DN VREG VBUS RREFEXT DI2_PIN3 NVCC_IPU7 VCC VCC GND GND GND GND GND GND GND VDDGP
CSI2_D17 CSI2_D16 CSI2_D15 CSI2_D14 ID VDDA33 NVCC_USBPHY NGND_USBPHY VCC GND GND GND GND GND GND GND VCC
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Table 113. 19 x 19 mm, 0.8 Pitch Ball Map (continued)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DRAM_DQM3 DRAM_SDQS3_B DRAM_SDQS3 DRAM_D26 DRAM_D25
H
DRAM_D27 DRAM_D23 DRAM_D22 DRAM_SDQS2_B DRAM_SDQS2
DRAM_D24 DRAM_D21 DRAM_D20 DRAM_DQM2 DRAM_D19
K
DRAM_D14 DRAM_D15 DRAM_D16 DRAM_D17 DRAM_D18
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 154 Preliminary--Subject to Change Without Notice Freescale Semiconductor
L
J
Package Information and Contact Assignments
M N R U DISP1_DAT3 P T DISP1_DAT5
23 22 21 20 19 18 17
CSI1_D19 CSI1_D18 CSI1_D15 CSI1_D14 DISP2_DAT1 NVCC_HS4_1 NVCC_HS6 NVCC_HS10 GND GND GND GND GND GND GND VDDA VCC
CSI1_D17 CSI1_D16 DISP1_DAT1 DISP1_DAT0 DISP2_DAT6 NVCC_HS4_2 VCC GND GND GND GND GND GND GND GND GND VCC
CSI1_D13 CSI1_D12 DISP2_DAT3 DISP2_DAT2 DISP2_DAT8 NVCC_IPU8 VCC VDDA GND GND GND GND GND GND GND GND VCC
CSI1_D11 CSI1_D10 DISP2_DAT0 DISP2_DAT9 DISP2_DAT11 NVCC_IPU9 VCC GND GND GND GND GND GND GND GND GND VDD_FUSE
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DISP1_DAT4
DISP1_DAT2
DISP2_DAT15
DI1_D0_CS
DI1_PIN13
POR_B
DISP2_DAT13
DISPB2_SER_DIN
NVCC_IPU2
NVCC_PER3
VCC
GND_ANA_PLL_B
Table 113. 19 x 19 mm, 0.8 Pitch Ball Map (continued)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
GND
NVCC_TV_BACK
NGND_TV_BACK
VREFOUT
NVCC_I2C
NVCC_SRTC_POW
VDDA
NVCC_PER14
VCC
NVCC_EMI
VCC
NVCC_EMI
VCC
NVCC_EMI
VCC
NVCC_EMI
VCC
NVCC_EMI
GND_DIG_PLL_A
GND_ANA_PLL_A
NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM NVCC_EMI_DRAM DRAM_D13 DRAM_D11 DRAM_D10 DRAM_DQM1 DRAM_D12
M
VDD_DIG_PLL_A
DRAM_D7 DRAM_SDQS1 DRAM_SDQS1_B DRAM_D8 DRAM_D9
N
DRAM_D5 DRAM_D6 DRAM_DQM0 DRAM_SDQS0 DRAM_SDQS0_B
P
VREF DRAM_D4 DRAM_D1 DRAM_D2 DRAM_D3
R
GND
DRAM_SDWE
DRAM_SDCLK_B
DRAM_A11
DRAM_SDCLK
EIM_SDBA1
DRAM_A14
DRAM_A12
DRAM_D0
DRAM_A13
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 155
U
T
Package Information and Contact Assignments
W A C GND V Y A A A B DI1_D1_CS
23 22 21 20 19 18 17
DISP2_DAT5
DISP2_DAT7
DISP2_DAT12
DISP2_DAT14
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DISP2_DAT4
DISP2_DAT10
DI1_PIN11
DI1_PIN12
BOOT_MODE1 DISPB2_SER_CLK
DISPB2_SER_DIO DISPB2_SER_RS
RESET_IN_B
CLK_SS
BOOT_MODE0
GND
TEST_MODE
FASTR_ANA
FASTR_DIG
CKIH2
EXTAL
XTAL
CKIH1
VDD_ANA_PLL_B
AHVSSRGB
AHVSSRGB
IOB_BACK
IOB
GND_DIG_PLL_B
VDD_DIG_PLL_B
AHVDDRGB
AHVDDRGB
IOG_BACK
IOG
NGND_OSC
NVCC_OSC
COMP
PMIC_RDY
IOR_BACK
IOR
Table 113. 19 x 19 mm, 0.8 Pitch Ball Map (continued)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TVDAC_DHVDD
PMIC_ON_REQ
CKIL
PMIC_INT_REQ
I2C1_DAT
JTAG_TMS
JTAG_TCK
I2C1_CLK
PMIC_STBY_REQ
JTAG_TDO
JTAG_DE_B
EIM_DA0
JTAG_MOD
JTAG_TRSTB
JTAG_TDI
EIM_DA2
EIM_DA3
EIM_DA4
EIM_DA1
EIM_DA7
EIM_DA5
EIM_DA6
EIM_DA8
EIM_DA10
EIM_EB0
EIM_EB1
EIM_DA9
EIM_DA12
EIM_DA14
EIM_D16
EIM_DA11
EIM_DA13
EIM_DA15
EIM_D18
EIM_D20
EIM_D22
EIM_EB2
EIM_D17
EIM_D19
EIM_D24
EIM_D26
EIM_D28
EIM_EB3
EIM_D21
EIM_D25
EIM_A16
EIM_A17
EIM_D30
EIM_D23
EIM_D27
EIM_D29
EIM_A19
EIM_A20
EIM_A18
NVCC_EMI
EIM_D31
EIM_CS2
EIM_OE
EIM_A22
EIM_A21
VDD_ANA_PLL_A
EIM_CS0
EIM_CS1
EIM_CS4
EIM_A25
EIM_A23
DRAM_A3
DRAM_SDCKE1
EIM_DTACK
EIM_CS5
EIM_A27
EIM_A24
DRAM_CAS
DRAM_A4
DRAM_CS0
EIM_BCLK
EIM_WAIT
EIM_A26
DRAM_A9
DRAM_A6
DRAM_CS1
DRAM_A2
EIM_RW
EIM_CS3
DRAM_A10
DRAM_A8
DRAM_A5
DRAM_A1
EIM_CRE
EIM_LBA
EIM_SDBA0
DRAM_RAS
DRAM_A7
DRAM_SDCKE0
DRAM_A0
GND
W
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 156 Preliminary--Subject to Change Without Notice Freescale Semiconductor
A C
V
Y
A A
A B
Revision History
5
Revision History
Table 114. i.MX51 Data Sheet Document Revision History
Rev. Number 1 Date 10/30/2009 Initial public release. Substantive Change(s)
Table 114 provides a revision history for this data sheet.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor Preliminary--Subject to Change Without Notice 157
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Document Number: IMX51AEC Rev. 1 11/2009
Preliminary--Subject to Change Without Notice

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